Kangxi Communications Technologies v. Skyworks Solutions Canada Inc

Prosecution History analysis

Examiner Search analysis

Invalidity Framework analysis

Petition

Petition Analysis

## 1. Case Identification
- Case Number: [IPR2025-00912](https://ai-lab.exparte.com/case/ptab/IPR2025-00912)
- Patent #: [7,409,200](https://ai-lab.exparte.com/patent/7409200)
- Filed: April 22, 2025
- Petitioner(s): KANGXI COMMUNICATION TECHNOLOGIES
- Patent Owner(s): [SKYWORKS SOLUTIONS, INC.](https://ai-lab.exparte.com/party/skyworks-solutions-inc)
- Challenged Claims: 1-2, 4, 6, 10-15, 18-20, 23-26, and 29-31

## 2. Patent Overview
- Title: MODULE INTEGRATION INTEGRATED CIRCUITS
- Brief Description: The [’200](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1001) patent relates to a technique for providing a high-performance, compact radio frequency (RF) module by partitioning a signal conditioning circuit (e.g., a power amplifier) into functional portions. These portions are integrated into separate semiconductor dies, often made from different materials (e.g., SiGe and GaAs) to optimize the performance of each portion, and then mounted on a common substrate to form a complete module.

## 3. Grounds for Unpatentability

#### Ground 1: Claims 1-2, 4, 10-13, 15, 18-20, 23-26, and 29-31 are obvious over Garlepp.
- **Prior Art Relied Upon:** U.S. Patent Application Publication No. 2003/0017809 ("[Garlepp](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1005)").
- **Core Argument for this Ground:** Petitioner argued that [Garlepp](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1005), which was not cited during the original prosecution, discloses the same circuit partitioning and multi-die integration arrangement claimed in the [’200](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1001) patent, rendering the claims obvious.
  - **Prior Art Mapping:** Petitioner asserted that [Garlepp](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1005) discloses an RF transceiver with a "receive path circuitry" (a first signal conditioning circuit) partitioned across two separate semiconductor dies (partitions 854 and 801) manufactured using different processes. Independent claim 1 was allegedly met because [Garlepp](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1005)'s receiver digital circuitry 851 (first portion) is on a first die (854), and the analog receive circuitry 839 (second portion) is on a second die (801). Petitioner contended it was conventional and obvious to mount these dies on a common substrate for support and interconnection. For dependent claims, Petitioner argued [Garlepp](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1005)'s disclosure of using CMOS for the digital die teaches a silicon-based technology (claim 4), and its use of separate fabrication processes for the analog and digital dies teaches that one process does not facilitate integration of the other (claim 10).
  - **Motivation to Combine (for §103 grounds):** The argument is that [Garlepp](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1005) alone renders the claims obvious. The motivation to add the claimed "substrate" was based on it being a well-known and conventional way of connecting and supporting semiconductor chipsets to provide a low-cost, low form-factor RF solution, a goal shared by [Garlepp](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1005).
  - **Expectation of Success (for §103 grounds):** A person of ordinary skill in the art (POSITA) would have had a high expectation of success in mounting [Garlepp](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1005)'s dies on a common substrate, as this was a routine packaging technique with predictable results.

#### Ground 2: Claims 1-2, 6, 10-15, 18-20, 23-26, and 29-31 are obvious over Magoon in view of Ngompe.
- **Prior Art Relied Upon:** R. Magoon et al., "A Single-Chip Quad-Band... Transceiver" (Dec. 2002) ("[Magoon](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1006)") and E. Ngompe et al., “Architecture and Performance Overview of a Highly Integrated... Module" (June 2003) ("[Ngompe](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1007)").
- **Core Argument for this Ground:** Petitioner argued that [Magoon](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1006) discloses a transceiver architecture with a partitioned transmitter circuit (on-chip and off-chip portions), and [Ngompe](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1007) teaches how to implement such a system in a multi-die module to optimize performance. Both references were authored by employees of the Patent Owner, [Skyworks Solutions, Inc.](https://ai-lab.exparte.com/party/skyworks-solutions-inc)
  - **Prior Art Mapping:** Petitioner argued that [Magoon](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1006) discloses a "transmitter path circuitry" (a first signal conditioning circuit) that is partitioned. The transmit PLLs/VCOs (second portion) are integrated on a BiCMOS chip (the second die), which provides signals to an off-chip power amplifier (PA) circuitry (the first portion). [Ngompe](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1007) was cited to teach that this off-chip PA would be implemented on a separate die, specifically a GaAs HBT PA (the first die), and that both dies would be mounted on a common laminate substrate. This combination allegedly teaches all elements of independent claim 1. For claim 6, [Magoon](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1006)'s PA circuitry was argued to be a power amplifier circuit for amplifying an input signal.
  - **Motivation to Combine (for §103 grounds):** A POSITA would combine [Magoon](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1006)'s transceiver design with [Ngompe](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1007)'s explicit multi-die packaging teachings to achieve a high-performance, low-cost, and compact module with a fast time-to-market. [Ngompe](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1007) expressly teaches using diverse die technologies (BiCMOS and GaAs) on a common substrate to "apply the optimum process for each function," directly addressing the problem solved by [Magoon](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1006)'s partitioned architecture.
  - **Expectation of Success (for §103 grounds):** A POSITA would have a reasonable expectation of success, as the combination involves applying [Ngompe](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1007)'s conventional multi-chip packaging techniques to [Magoon](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1006)'s known RF transceiver architecture to achieve predictable benefits in cost, size, and performance.

## 4. Relief Requested
- Petitioner requested institution of an inter partes review and cancellation of claims 1-2, 4, 6, 10-15, 18-20, 23-26, and 29-31 of the [’200](https://ai-lab.exparte.com/case/ptab/IPR2025-00912/doc/1001) patent as unpatentable under 35 U.S.C. §103.

Skyworks' RF module patent faces obviousness challenge to 23 claims based on Garlepp & Magoon art teaching multi-die circuit partitioning.