PTAB

IPR2025-00994

Samsung Electronics Co Ltd v. W&Wsens Devices Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Photodetector Device
  • Brief Description: The ’360 patent describes a photodetector device designed to enhance photon absorption using microstructures. The technology involves an array of pillars with deliberately formed in-pillar holes on a semiconductor substrate, which allegedly increases light absorption by at least 10% compared to a device without such microstructures.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kuboi and Shinohara - Claims 1, 3, and 5-6 are obvious over Kuboi in view of Shinohara.

  • Prior Art Relied Upon: Kuboi (Application # 2012/0049044) and Shinohara (Application # 2012/0033119).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kuboi, a CMOS imaging device, discloses the core features of claim 1, including a photodetector on a semiconductor substrate with a laterally extending array of pillars (pixels) having rectangular cross-sections. Kuboi’s pillars are comprised of a first doped semiconductor region (p+ region 18), an intermediate region (n-type region 16), and a second doped region (n+ region 17). Kuboi also teaches deliberately formed "in-pillar holes" (holes 38) filled with a solid dielectric material (electron blocking film 21 and photoelectric conversion film 13). Petitioner contended that Kuboi discloses top and bottom electrical contacts and a base dielectric region below the pillars. To the extent Kuboi does not explicitly teach a solid dielectric between adjacent pillars, Shinohara was cited. Shinohara teaches an imaging device with a solid dielectric insulating film (insulating film 69, such as silicon oxide) filled in voids between pixels to improve electrical insulation and prevent light leakage. For the monolithic integration limitation, Petitioner argued that while Kuboi discloses forming the pixel and logic circuits on the same substrate, Shinohara explicitly teaches monolithic integration of the pixel array and electronic circuits on a single substrate.
    • Motivation to Combine: A POSITA would combine Shinohara’s solid dielectric insulating film with Kuboi’s pixel separation region to solve the known problems of charge leakage and color mixture between adjacent pixels. Shinohara explicitly teaches these benefits. Additionally, a POSITA would be motivated to apply Shinohara’s monolithic integration method to Kuboi’s device to achieve well-known advantages such as reduced manufacturing cost, smaller package size, and improved signal integrity.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in making these combinations, as they involved applying known techniques to similar imaging devices to achieve predictable improvements in performance and manufacturability.
    • Key Aspects: The argument for claim 3 (plurality of in-pillar holes) and claims 5-6 (hole depth and extension into intermediate material) was based directly on Kuboi’s disclosure of forming multiple holes (in a stripe shape) that extend through the device's stacked semiconductor layers to a depth of about 1400 nm.

Ground 2: Obviousness over Yu or Yu and Shinohara - Claims 1 and 8-9 are obvious over Yu, or Yu in view of Shinohara.

  • Prior Art Relied Upon: Yu (Application # 2012/0153124) and Shinohara (Application # 2012/0033119).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Yu, which describes an image sensor with nanopillars, discloses all limitations of claim 1. Yu’s device is formed on a semiconductor substrate and includes an array of pixels, which Petitioner argued correspond to the claimed "pillars." These pillars are arranged in rows and columns and have a rectangular cross-section. Yu’s pillars are formed from a first doped layer (junction layer 1040), an intermediate layer (epi layer 1030), and a second doped layer (HDL layer 1020). Yu also discloses a cladding of solid dielectric (silicon nitride) between adjacent pillars. Petitioner argued that the spaces created by deep-etching to form Yu's nanopillars are the claimed "in-pillar holes" and are filled with a solid dielectric (silicon oxide). Yu further discloses top and bottom electrical contacts, a base dielectric region (oxide layer 1010), and the claimed dimensional ranges for pillar spacing and intermediate layer thickness. For claim 8, Petitioner argued that Yu’s method of forming square nanopillars via perpendicular trench etching inherently creates overlapping in-pillar holes. For claim 9, Petitioner argued Yu’s readout lines (formed from the second doped material) are laterally continuous regions coupled to multiple pillars.
    • Motivation to Combine (for Shinohara): This combination was presented as an alternative. If the Board were to find that Yu does not teach monolithic integration of its sensor and control circuits, Shinohara was cited for its explicit teaching of forming a pixel region and peripheral circuit portions on the same substrate. The motivation to combine would be to gain the widely recognized benefits of single-chip integration, such as lower cost and improved performance.
    • Expectation of Success: A POSITA would expect success in applying Shinohara's conventional monolithic integration techniques to Yu's image sensor, as it was a standard approach for improving such devices.

4. Relief Requested

  • Petitioner requests institution of IPR and cancellation of claims 1, 3, 5-6, and 8-9 of Patent 11,621,360 as unpatentable.