PTAB

IPR2025-01019

OmniVision Technologies Inc v. Re Secured Networks LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: HIGH SENSITIVITY SNAP SHOT CMOS IMAGE SENSOR
  • Brief Description: The ’651 patent discloses solid-state imaging devices, such as CMOS imagers, that use multiple analog-to-digital (A/D) converters to process signals from different color channels. The patent describes an architecture with pixels in a Bayer filter pattern where one A/D converter processes red and blue channel signals, a second A/D converter processes green channel signals, and a color interpolation circuit combines the resulting digital signals.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1 and 18 by Isogai

  • Prior Art Relied Upon: Isogai (Japanese Patent Application Pub. No. 2000-12819).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Isogai discloses every element of independent claims 1 and 18. Isogai teaches a solid-state image sensing device with red, blue, and green pixels arranged in a color filter array. It explicitly discloses separating the outputs into a green signal channel and a combined red/blue signal channel, with each channel being processed by its own dedicated A/D converter (AD 80 for green, AD 81 for red/blue). Isogai’s signal processing unit (89) for a Bayer arrangement performs pixel interpolation, which Petitioner asserted meets the limitation of a "color interpolation circuit for combining the first, second, third and fourth digital signals" to produce a final color image.
    • Key Aspects: This ground asserted that Isogai’s two-channel, two-A/D converter architecture for processing Bayer pattern pixel data directly reads on the core architectural claims of the ’651 patent.

Ground 2: Obviousness of Claims 2-5 and 19-22 over Isogai in view of Neter

  • Prior Art Relied Upon: Isogai (Japanese Patent Application Pub. No. 2000-12819) and Neter (Patent 7,133,073).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted Isogai teaches the base solid-state imaging device of claim 1. Dependent claims 2 and 3 require an "error compensation circuit" for correcting gain and fixed pattern noise, respectively. Neter was cited as teaching these features. Neter discloses using programmable gain amplifiers for color compensation to correct for different sensitivities among color filters. It also teaches fixed pattern noise reduction by subtracting a dark current signal from the active pixel signal. Claims 4 and 5, which recite single-chip and two-chip configurations, were argued to be obvious design choices also taught by Neter, which discloses that processing components can be on-chip or off-chip.
    • Motivation to Combine: A POSITA would combine Isogai's imaging architecture with Neter's error correction techniques to solve known problems in the art. Implementing Neter's gain correction would improve Isogai's dynamic range and white balancing, and adding its fixed pattern noise reduction would predictably increase image quality by reducing signal contamination.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because combining Neter's well-understood error and noise correction circuits with Isogai's standard imager architecture involved applying known solutions to achieve predictable results.

Ground 3: Obviousness of Claims 2-5 and 19-22 over Isogai in view of Fossum

  • Prior Art Relied Upon: Isogai (Japanese Patent Application Pub. No. 2000-12819) and Fossum (Patent 6,704,049).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative to Ground 2, again starting with Isogai as the base reference. For the "error compensation circuit" limitations of claims 2 and 3, Petitioner relied on Fossum. Fossum teaches an analog conditioning circuit that provides "gain control" for pixel outputs, which Petitioner equated with the claimed gain correction. Fossum also teaches that its analog conditioning circuitry performs correlated double sampling, a known technique for reducing fixed pattern noise, thereby satisfying the limitation of claim 3. Similar to Neter, Fossum discloses both single-chip imagers and the use of a separate DSP chip for color interpolation, rendering the configurations of claims 4 and 5 obvious design choices.
    • Motivation to Combine: A POSITA would have been motivated to incorporate Fossum's analog conditioning circuitry into Isogai's device to improve overall system performance. Adding gain control and correlated double sampling were known methods to enhance image quality, a common goal in sensor design.
    • Expectation of Success: The combination would have yielded predictable results, as it involved integrating known signal conditioning techniques (Fossum) into a conventional imager design (Isogai).
  • Additional Grounds: Petitioner asserted additional challenges including Ground 4, alleging anticipation of claims 1, 18 and others by Inuiya (Patent 5,982,984). Grounds 5 and 6 mirrored Grounds 2 and 3, asserting the obviousness of claims 4-5 and 21-22 over Inuiya in view of Neter and Fossum, respectively, based on similar design choice and performance improvement rationales.

4. Key Claim Construction Positions

  • "circuit": Petitioner asserted that in the context of the "color interpolation circuit," this term connotes a hardware implementation, opposing a broader construction that would include firmware or software.
  • "combining the first, second, third and fourth digital signals": Petitioner argued this phrase requires that the color interpolation circuit actually combines all four specified digital signals, not just a subset. For the petition, Petitioner stated it applied these narrower proposed constructions.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-5 and 18-22 of the ’651 patent as unpatentable.