OmniVision Technologies, Inc.

Petition

Petition summary

## 1. Case Identification
- Case Number: [IPR2025-01019](https://ai-lab.exparte.com/case/ptab/IPR2025-01019)
- Patent #: [6,838,651](https://ai-lab.exparte.com/patent/6838651)
- Filed: May 20, 2025
- Petitioner(s): [OmniVision Technologies, Inc.](https://ai-lab.exparte.com/party/omnivision-technologies-inc)
- Patent Owner(s): [RE Secured Networks, LLC](https://ai-lab.exparte.com/party/re-secured-networks-llc)
- Challenged Claims: 1-5 and 18-22

## 2. Patent Overview
- Title: HIGH SENSITIVITY SNAP SHOT CMOS IMAGE SENSOR
- Brief Description: The ’651 patent discloses a Complementary Metal Oxide Semiconductor (CMOS) solid-state imaging device. The device uses pixels arranged in a Bayer filter pattern and employs two separate analog-to-digital (A/D) converters—one for red and blue color channels and a second for green color channels—whose outputs are combined by a color interpolation circuit.

## 3. Grounds for Unpatentability

#### Ground 1: Anticipation over Isogai - Claims 1 and 18 are anticipated by Isogai under 35 U.S.C. §102.
  - **Prior Art Relied Upon:** Japanese Patent Application Pub. No. 2000-12819 ("[Isogai](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1005)").
  - **Core Argument for this Ground:**
    - **Prior Art Mapping:** Petitioner argued that [Isogai](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1005) discloses a solid-state imaging device that meets every limitation of independent claims 1 and 18. [Isogai](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1005) allegedly teaches an image sensor with red, blue, and green pixels arranged in a checkered pattern (claim 1[a-d]). Petitioner contended that Isogai's signal processing system uses two separate A/D converters: converter 81 processes the time-series red and blue pixel signals into first and second digital signals (claim 1[e]), while converter 80 processes the green pixel signals into third and fourth digital signals (claim 1[f]). Finally, Petitioner asserted that Isogai’s "signal processing unit for Bayer arrangement" (89) is a color interpolation circuit that combines these four digital signals to perform pixel interpolation and generate RGB color signals, meeting the final limitation of the claims (claim 1[g]).

#### Ground 2: Obviousness over Isogai in view of Neter - Claims 2-5 and 19-22 are obvious over Isogai in view of Neter under 35 U.S.C. §103.
  - **Prior Art Relied Upon:** [Isogai](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1005), U.S. Patent No. 7,133,073 ("[Neter](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1007)").
  - **Core Argument for this Ground:**
    - **Prior Art Mapping:** Petitioner argued that while [Isogai](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1005) provides the base system of claim 1, it does not explicitly disclose the "error compensation circuit" required by dependent claims 2 and 3. [Neter](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1007), which also describes Bayer pattern image sensors, allegedly remedies this deficiency by teaching circuits for both gain correction (claim 2) and fixed pattern noise offset correction (claim 3). [Neter](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1007) discloses using programmable gain amplifiers for color-specific amplification to compensate for variations in color filter response. It also teaches using dark current removal circuitry (e.g., subtracting dark pixel values) to correct for fixed pattern noise. For claims 4 and 5, which recite disposing components on one or two chips, Petitioner argued [Neter](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1007) discloses that placing A/D converters and processing circuitry on-chip or off-chip is a known design choice.
    - **Motivation to Combine:** A Person of Ordinary Skill in the Art (POSA) implementing Isogai's sensor would have been motivated to look to a reference like [Neter](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1007) to solve known problems of color compensation and fixed pattern noise. A POSA would combine Isogai's sensor with Neter's error correction techniques to achieve the predictable benefits of improved dynamic range, white balancing, and overall image quality. The decision to place components on one or two chips was a known design trade-off between integration complexity and system flexibility.
    - **Expectation of Success:** A POSA would have a reasonable expectation of success in combining these elements, as it involved applying known error correction techniques (gain and offset correction) and well-understood chip layout strategies to a conventional image sensor architecture to achieve predictable improvements.

#### Ground 3: Anticipation over Inuiya - Claims 1 and 18 are anticipated by Inuiya under §102.
  - **Prior Art Relied Upon:** U.S. Patent No. 5,982,984 ("[Inuiya](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1006)").
  - **Core Argument for this Ground:**
    - **Prior Art Mapping:** Petitioner asserted that [Inuiya](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1006) discloses a digital video tape recorder with a solid-state electronic image sensing device (CCD 100) that anticipates claims 1 and 18. Inuiya's CCD 100 has red, blue, and green pixels with outputs. Petitioner contended that [Inuiya](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1006) teaches a first A/D converter (103) that receives and sequentially converts the red and blue pixel outputs into first and second digital signals, and a second A/D converter (104) that converts the green pixel outputs into third and fourth digital signals. Petitioner argued that Inuiya’s color processing block (114), which receives these digital signals and processes them to generate luminance and color difference data, constitutes the claimed "color interpolation circuit for combining" the signals.

- **Additional Grounds:** Petitioner asserted additional obviousness challenges, including grounds that claims 2-5 and 19-22 are obvious over [Isogai](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1005) in view of [Fossum](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1008) (Patent 6,704,049), and that claims 4-5 and 21-22 are obvious over [Inuiya](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1006) in view of [Neter](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1007) or [Fossum](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1008). These grounds relied on similar arguments that [Fossum](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1008) and [Neter](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1007) provide known solutions for error compensation and multi-chip/single-chip design choices that a POSA would have been motivated to apply to the base systems of [Isogai](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1005) or [Inuiya](https://ai-lab.exparte.com/case/ptab/IPR2025-01019/doc/1006).

## 4. Key Claim Construction Positions
- Petitioner asserted that for the purposes of the petition, it applied its own narrower proposed constructions from co-pending district court litigation.
- **"circuit":** Petitioner contended this term, as used in "color interpolation circuit," connotes a hardware implementation. This is narrower than the Patent Owner's proposed construction which includes firmware or software.
- **"combining the first, second, third and fourth digital signals":** Petitioner asserted this requires combining all four signals. This is critical to its anticipation arguments, as the prior art allegedly shows processing units that take all four signal types as inputs for interpolation.

## 5. Relief Requested
- Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-5 and 18-22 of the ’651 patent as unpatentable.

OmniVision challenges CMOS image sensor patent: Isogai & Inuiya cited for anticipation & obviousness against 10 claims on dual A/D converter design.