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IPR2025-01076

United Microelectronics Corp v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method of Manufacturing Semiconductor Device
  • Brief Description: The ’227 patent relates to techniques for improving the driving power and reliability of a metal-insulator-semiconductor field-effect transistor (MISFET). The invention focuses on a double-sidewall structure where a high-k gate insulating film extends continuously from under the gate electrode to under at least a first insulating sidewall, with the film being thicker under the gate electrode than under the sidewall.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 2 are anticipated by Kajiyama.

  • Prior Art Relied Upon: Kajiyama (JP Publication # JP2003-258241).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kajiyama discloses every limitation of claims 1 and 2. Kajiyama’s field-effect transistor (FET) is described with a gate electrode, a first insulating sidewall, and a second insulating sidewall formed over the first. A high-k gate insulating film is formed on the substrate. Petitioner asserted that Kajiyama’s figures and described fabrication process—where the high-k film is etched after the gate electrode is formed—inherently result in a structure where the high-k film is thicker under the gate electrode than in adjacent areas. The process further shows the film extending continuously under the first sidewall but being removed before the formation of the second sidewall, thus not extending under the second sidewall as required by claim 2.

Ground 2: Claims 1 and 2 are obvious over Matsumoto.

  • Prior Art Relied Upon: Matsumoto (Application # 2003/0025135).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Matsumoto’s first and fourth embodiments describe a MOSFET with a multilayer insulating sidewall structure that meets the limitations of claims 1 and 2. Matsumoto discloses a gate electrode with a first insulating sidewall (silicon oxide film 8) and a second insulating sidewall (silicon nitride film 9). A high-k gate insulating film (film 6) is shown extending continuously from under the gate electrode to under the first insulating sidewall. In the fourth embodiment, this film explicitly does not extend under the second sidewall.
    • Motivation to Combine (for §103 grounds): As a single-reference ground, the obviousness argument centered on the teachings of Matsumoto itself. Petitioner argued that Matsumoto’s described fabrication process, which involves etching the high-k dielectric film after forming the gate electrode, would have been understood by a Person of Ordinary Skill in the Art (POSITA) to result in a thinner film under the sidewalls compared to the portion protected by the gate electrode. This predictable result of a standard manufacturing step rendered the claimed thickness variation obvious.

Ground 3: Claims 7, 8, and 14 are obvious over Matsumoto in view of Wang.

  • Prior Art Relied Upon: Matsumoto (Application # 2003/0025135) and Wang (Application # 2006/0131672).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Matsumoto teaches the core structure of claims 1 and 2, and Wang supplies the additional limitations of claims 7, 8, and 14. Claim 7 adds a "buffer insulating film" between the substrate and the high-k film, which claim 8 specifies is a silicon oxide or silicon oxynitride film. Claim 14 requires the high-k film to be a hafnium (Hf) based oxide. Wang explicitly teaches using a buffer layer (preferably silicon oxide) to prevent undesirable interactions between a high-k dielectric and the silicon substrate, thereby improving carrier mobility. Wang also expressly lists Hf-based oxides (e.g., HfO2) as a preferred material for the high-k gate dielectric due to its superior thermal stability and electrical properties.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Wang’s teachings with Matsumoto’s device to solve a known problem. Wang provides the express rationale of using a buffer layer to suppress interface degradation and improve performance, which directly aligns with Matsumoto's stated goal of reducing malfunctions. Selecting HfO2 from Wang’s list of high-k materials was presented as a simple and advantageous choice for a POSITA seeking to optimize the device.
    • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success, as Wang describes using conventional and well-established deposition methods (e.g., CVD, ALD) for its buffer and high-k layers, which were fully compatible with the fabrication processes disclosed in Matsumoto.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 7-8 are obvious over Matsumoto in view of Mutou (Application # 2005/0045938), and that claim 14 is obvious over Matsumoto in view of Ono (Application # 2005/0051856) or over Kajiyama alone. These grounds relied on similar rationales, substituting Wang with other references that also taught buffer layers or Hf-based oxides to improve transistor performance.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-2, 7-8, and 14 of Patent 7,579,227 as unpatentable.