Samsung Electronics America Inc v. Radian Memory Systems LLC

1. Case Identification

• Case #: IPR2025-01289
• Patent #: 11,681,614
• Filed: July 14, 2025
• Petitioner(s): Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc.
• Patent Owner(s): Radian Memory Systems LLC
• Challenged Claims: 1-30

2. Patent Overview

• Title: Storage Device With Subdivisions, Subdivision Query, And Write Operations
• Brief Description: The ’614 patent describes a solid-state drive (SSD) memory system where management responsibilities are shared between the device's internal controller and an external host system. The technology involves organizing flash memory into "subdivisions" or "zones" and allowing the host to query the device for information about these zones to initiate maintenance operations like garbage collection and wear leveling.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ellis and Son - Claims 1-2 and 4-8 are obvious over Ellis in view of Son.

• Prior Art Relied Upon: Ellis (Patent 9,239,781) and Son (Application # 2012/0096217).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ellis taught the core architecture of a storage device with flash memory subdivided into logical groupings called "superblocks" (the claimed "zones"), which are comprised of erase blocks ("erase units"). Ellis also disclosed that memory operations could be shared between the memory controller and the host system. However, Petitioner contended Ellis did not explicitly teach a host querying the device for zone information or issuing specific management commands. Son was argued to supply these missing elements by disclosing an SSD management module on a host device that "queries" the SSD controller for superblock metadata (including state, wear count, and page availability) to initiate maintenance operations like garbage collection and wear leveling.
  • Motivation to Combine: Petitioner asserted a person of ordinary skill in the art (POSITA) would combine Ellis and Son because both references address optimizing NAND flash memory management. Son was presented as an improvement to systems like Ellis, explaining that moving management logic to the host, which has file system information, overcomes inefficiencies of conventional controller-only designs. This combination would offload the SSD controller and allow for more informed management decisions, a known goal in the art.
  • Expectation of Success: Petitioner argued a POSITA would have a high expectation of success, as the combination represented a straightforward implementation of a known shared management technique (from Son) onto a similar flash memory architecture organized into superblocks (from Ellis).

Ground 2: Obviousness over Ellis, Son, and Olbrich - Claims 3, 10-14, 16-19, and 21-29 are obvious over Ellis and Son in view of Olbrich.

• Prior Art Relied Upon: Ellis (Patent 9,239,781), Son (Application # 2012/0096217), and Olbrich (Patent 8,621,137).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Ellis and Son combination to address claims requiring multi-plane write operations that use a "common page address" (e.g., claim 3). Petitioner argued that while Ellis taught concurrent multi-plane writes for improved performance, it did not explicitly disclose using a common page address. Olbrich was introduced to teach this specific limitation, as it disclosed a multi-plane command that writes to pages on different dies using the "same address location."
  • Motivation to Combine: A POSITA would have been motivated to incorporate Olbrich’s teaching into the Ellis/Son system to further improve performance. Using a common page address for multi-plane commands was a known technique for increasing parallelism and improving the overall performance of SSDs, a primary objective for designers.
  • Expectation of Success: The combination was presented as the predictable application of a known technique (common page address multi-plane writes from Olbrich) to an existing system (the Ellis/Son combination) to achieve a known benefit (improved parallelism).

Ground 3: Obviousness over Takeo, Son, and Sinclair - Claims 1-2 and 4-8 are obvious over Takeo in view of Son and Sinclair.

• Prior Art Relied Upon: Takeo (JP Publication No. JP2008-176606), Son (Application # 2012/0096217), and Sinclair (WO 2008/082996).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground presented an alternative foundation for obviousness. Petitioner argued Takeo served as the primary reference, disclosing a flash memory system subdivided into "zones" and a "vendor command" for a host to query and acquire internal information about these zones. As with Ground 1, Son was added to teach host-initiated management commands based on this queried data. Sinclair was introduced to teach organizing erase blocks across multiple planes into "metablocks" ("zones") that can be written to and erased together, satisfying limitations related to multi-plane operations.
  • Motivation to Combine: Petitioner asserted a POSITA would combine Takeo with Son to add necessary, but absent, management functions like wear leveling. The resulting system would then be combined with Sinclair's multi-plane architecture to increase parallelism and performance, which is a key factor for SSD efficiency. Sinclair explicitly taught that its "metablock" structure improves performance.
  • Expectation of Success: The combination was argued to be a straightforward implementation of known techniques. Combining Takeo with Son’s host-side management and Sinclair’s multi-plane architecture would predictably result in a more efficient and higher-performing storage device.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations of Ellis, Son, Olbrich, and Yamada (Application # 2011/0271032A1) for claims 9, 15, 20, and 30, and combinations of Takeo, Son, Sinclair, Olbrich, and Yamada for claims 3, 9-20, and 21-30. These grounds relied on similar modification theories, adding references to teach specific features, such as Yamada's disclosure of a controller providing an asynchronous recommendation to the host to perform maintenance when a metadata threshold is exceeded.

4. Relief Requested

• Petitioner requests the institution of an inter partes review and the cancellation of claims 1-30 of the ’614 patent as unpatentable.