Samsung Electronics America, Inc. et al.

Prosecution History analysis

Examiner Search analysis

Invalidity Framework analysis

Petition

Petition Analysis

## 1. Case Identification
- Case #: [IPR2025-01289](https://ai-lab.exparte.com/case/ptab/IPR2025-01289)
- Patent #: [11,681,614](https://ai-lab.exparte.com/patent/11681614)
- Filed: July 14, 2025
- Petitioner(s): [Samsung Electronics Co., Ltd.](https://ai-lab.exparte.com/party/samsung-electronics-america-inc) and [Samsung Electronics America, Inc.](https://ai-lab.exparte.com/party/samsung-electronics-america-inc)
- Patent Owner(s): [Radian Memory Systems LLC](https://ai-lab.exparte.com/party/radian-memory-systems-llc)
- Challenged Claims: 1-30

## 2. Patent Overview
- Title: Storage Device With Subdivisions, Subdivision Query, And Write Operations
- Brief Description: The [’614 patent](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1001) describes a flash memory storage system, such as a solid-state drive (SSD), where memory management responsibilities are shared between the device’s internal controller and an external host system. The technology involves dividing the flash memory into logical "zones," allowing the host to query the controller for metadata about these zones (e.g., state, size, available pages), and using this information to issue management commands for operations like garbage collection and wear leveling.

## 3. Grounds for Unpatentability

#### Ground 1: Obviousness over Ellis and Son - Claims 1-2 and 4-8 are obvious over Ellis in view of Son.
- **Prior Art Relied Upon:** [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004) (Patent 9,239,781) and [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006) (Application # 2012/0096217).
- **Core Argument for this Ground:**
    - **Prior Art Mapping:** Petitioner argued that [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004) discloses a storage device with flash memory subdivided into "superblocks" (analogous to the claimed "zones"), which are groups of erase units. [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004) further teaches that these superblocks are associated with logical address ranges and metadata, and suggests that management functions can be shared between the device controller and a host system. To the extent [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004) does not explicitly detail the host's role, Petitioner asserted that [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006) remedies this by describing a shared management architecture where the host actively queries the SSD controller for detailed superblock metadata (e.g., state, valid page count, wear count) and uses that information to issue management commands for garbage collection and wear leveling.
    - **Motivation to Combine:** A POSITA would combine [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004) and [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006) because both references address the optimization of NAND flash memory management. Petitioner asserted that [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006) explicitly describes improving conventional systems by moving management logic to the host to relieve the SSD controller and leverage file system information, which directly addresses the architecture suggested in [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004). Combining [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006)'s host-driven query and command system with [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004)'s superblock structure was presented as a predictable way to improve system efficiency and performance.
    - **Expectation of Success:** Petitioner argued that a POSITA would have a reasonable expectation of success, as the combination represents a straightforward implementation of known shared management principles on similar flash memory architectures to achieve predictable benefits.

#### Ground 2: Obviousness over Takeo, Son, and Sinclair - Claims 1-2 and 4-8 are obvious over Takeo in view of Son and Sinclair.
- **Prior Art Relied Upon:** [Takeo](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1012) (Japanese Publication No. JP2008-176606), [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006) (Application # 2012/0096217), and [Sinclair](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1005) (WO 2008/082996).
- **Core Argument for this Ground:**
    - **Prior Art Mapping:** This ground presents an alternative to [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004) as the base reference. Petitioner argued that [Takeo](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1012) teaches a flash memory system divided into "zones," where the controller can return internal information (e.g., the number of empty blocks per zone) to a host in response to a "vendor command" (a query). [Sinclair](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1005) was cited for its teaching of grouping erase blocks from multiple physical planes into a single "metablock" (a zone) to enable concurrent, parallel write operations for improved performance. As in the first ground, [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006) was argued to supply the teaching of a host issuing explicit management commands for wear leveling and garbage collection based on queried metadata.
    - **Motivation to Combine:** A POSITA would be motivated to combine [Takeo](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1012)'s zone-based query system with [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006)'s host-driven management logic to create a more capable and flexible shared management architecture. [Sinclair](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1005) would be incorporated to enhance the performance of the [Takeo](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1012) system by introducing multi-plane parallelism, a well-known objective in SSD design. The combination would allow the host to intelligently manage a higher-performing, parallel-access memory device.
    - **Expectation of Success:** Petitioner contended that success would be expected because the combination involves applying known techniques (shared management from [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006), parallel architecture from [Sinclair](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1005)) to a known system ([Takeo](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1012)) to achieve the predictable results of improved management efficiency and increased data throughput.

#### Ground 3: Obviousness over Ellis, Son, Olbrich, and Yamada - Claims 9, 15, 20, and 30 are obvious.
- **Prior Art Relied Upon:** [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004) (Patent 9,239,781), [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006) (Application # 2012/0096217), [Olbrich](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1010) (Patent 8,621,137), and [Yamada](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1015) (Application # 2011/0271032).
- **Core Argument for this Ground:**
    - **Prior Art Mapping:** This ground builds on the [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004)/[Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006) combination to challenge claims requiring the storage device to trigger host-side maintenance. Specifically, claims 9 and 15 require the device to generate metadata (time since last write or erase count, respectively), compare it to a threshold, and then "recommend" that the host issue a maintenance command. Petitioner argued that [Yamada](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1015) teaches this precise mechanism: a memory controller internally tracks a condition (e.g., error count), compares it to a "criterion value" (threshold), and sends a "maintenance request" to the host, prompting the host to schedule a maintenance operation like data refresh or wear leveling.
    - **Motivation to Combine:** A POSITA would be motivated to integrate [Yamada](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1015)'s threshold-based notification system into the shared-management architecture of [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004)/[Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006). This combination allows the device to autonomously monitor its health (e.g., data retention risk, block wear) and proactively request maintenance from the host without exposing sensitive internal metrics or requiring the host to constantly poll the device. Petitioner argued this improves data integrity and optimizes device longevity, which are strong motivators for a designer.
    - **Expectation of Success:** This combination was argued to be a predictable integration of complementary functionalities. The [Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004)/[Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006) framework provides the host-controller communication channel, and [Yamada](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1015) provides a specific, well-understood protocol for triggering actions over that channel.

- **Additional Grounds:** Petitioner asserted additional obviousness challenges against all claims (1-30) based on various combinations of the primary references ([Ellis](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1004), [Takeo](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1012), [Son](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1006), [Sinclair](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1005), [Olbrich](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1010), [Yamada](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1015)), relying on similar arguments regarding the implementation of shared memory management, multi-plane operations for parallelism, and metadata-based maintenance triggers.

## 4. Relief Requested
- Petitioner requests institution of an inter partes review and cancellation of claims 1-30 of the [’614 patent](https://ai-lab.exparte.com/case/ptab/IPR2025-01289/doc/1001) as unpatentable.

Samsung targets SSD memory management patent: prior art cited for all 30 claims as obvious over shared host-controller management architecture.