PTAB

IPR2025-01350

Samsung Electronics Co Ltd v. Radian Memory Systems LLC

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petition

1. Case Identification

2. Patent Overview

  • Title: Storage Device with Host-Cooperative Maintenance
  • Brief Description: The ’801 patent describes a storage device with NAND flash memory and a memory controller. The controller manages data by mapping non-overlapping logical address ranges to physical subdivisions of the memory, tracking the fullness of these subdivisions, and providing metadata to a host system to facilitate cooperative memory maintenance operations.

3. Grounds for Unpatentability

Ground 1: Obviousness over Sinclair and Yamada - Claims 1-4, 6, 9-16, 21, and 24 are obvious over Sinclair in view of Yamada.

  • Prior Art Relied Upon: Sinclair (Application # 2009/0271,562) and Yamada (Application # 2011/0271,032).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sinclair discloses a solid-state drive with a memory controller that manages NAND flash memory organized into "megablocks" (subdivisions) and "metablocks" (erase blocks). Sinclair’s controller maps logical addresses to these subdivisions, receives write requests, and programs data sequentially into an open write megablock. Critically, Sinclair tracks the extent to which metablocks are full by categorizing them as "white" (empty), "red" (completely full), or "pink" (partially full), which Petitioner contended meets the limitation of updating information on subdivision fullness. Sinclair also initiates a "flush operation"—a maintenance request to free up space by relocating data from pink blocks and erasing them—when the number of available white blocks is low. Petitioner asserted this flush operation meets the limitation of acting on a maintenance request to physically erase a portion of the memory.
    • Motivation to Combine: Petitioner contended that while Sinclair’s controller autonomously manages the flush operation, it also suggests that the host can be involved, such as by selecting pink blocks for flushing. To the extent Sinclair does not explicitly teach a host-issued maintenance request, Petitioner argued a person of ordinary skill in the art (POSITA) would combine Sinclair with Yamada. Yamada explicitly teaches moving maintenance functions to the host to improve system performance by allowing the host to consider device-wide conditions, like power consumption, before initiating resource-intensive operations. A POSITA would combine Yamada’s host-centric command generation with Sinclair’s memory management system to create a more efficient cooperative memory architecture.
    • Expectation of Success: Petitioner asserted a POSITA would have a reasonable expectation of success because Sinclair already discloses a framework for host-controller communication regarding block status. Integrating Yamada's teachings would involve modifying this existing interface to allow the host to initiate a maintenance command, which was a known and predictable design modification in the art.

Ground 2: Obviousness over Terasaki and Yamada - Claims 1, 9, and 13-15 are obvious over Terasaki in view of Yamada.

  • Prior Art Relied Upon: Terasaki (Certified Translation of JP2005018490A) and Yamada (Application # 2011/0271,032).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner presented Terasaki as an alternative primary reference that teaches a flash memory system with a controller managing physical subdivisions called "zones." Terasaki’s controller receives write commands from a host and maps logical block addresses (LBAs) to these zones. It maintains a "zone management table" that tracks the status of each zone (e.g., write state, erased, erase request), which Petitioner argued corresponds to the claimed information representing the extent to which erase blocks are full. Terasaki also discloses initiating an erase process for zones flagged with an "erase request," which Petitioner equated to fulfilling a maintenance request issued by the host during a subsequent write operation. Metadata, such as erase counts and error collection codes (ECC), is used to manage wear-leveling.
    • Motivation to Combine: The motivation to combine Terasaki with Yamada mirrors that of Ground 1. Petitioner argued that Terasaki’s maintenance is initiated by the controller in response to host write commands. A POSITA would have been motivated to modify Terasaki by incorporating Yamada’s teaching of having the host directly issue maintenance requests. This modification would allow the host to schedule erase operations more intelligently based on system-level factors, thereby improving overall efficiency and longevity of the storage device, a well-understood goal in the field.
    • Expectation of Success: Petitioner claimed success would be expected because Terasaki's system already includes a host interface for exchanging commands, status, and address information. Modifying this interface to accept an explicit maintenance command from the host, as taught by Yamada, would be a straightforward implementation for a POSITA.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for claim 22 (over Sinclair, Yamada, and Olbrich for using a common address offset in multi-plane write commands) and claim 23 (over Sinclair, Yamada, Sinclair-II, and Yu for bad block management in connection with physical erasure).

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 6, 9-16, and 21-24 of the ’801 patent as unpatentable.