PTAB

IPR2025-01377

Samsung Electronics Co Ltd v. Radian Memory Systems LLC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Flash Memory Controller with Logical-to-Physical Address Translation
  • Brief Description: The ’656 patent discloses systems and methods for a flash memory controller that performs logical-to-physical address translation. The patent purports to achieve negligible translation time through "hierarchal address virtualization," where a logical address is translated into sub-addresses for virtual structures (e.g., virtual erase unit) before being translated to physical addresses.

3. Grounds for Unpatentability

Ground I: Obviousness over Reiter and T10 Standards - Claims 1-12, 16, and 20-23 are obvious over Reiter in view of ZBC, SBC-4, and SPC-4.

  • Prior Art Relied Upon: Reiter (Patent 8,301,861) and T10 Standards (Zoned Block Commands ("ZBC"), SCSI Block Commands-4 ("SBC-4"), and SCSI Primary Commands-4 ("SPC-4") working drafts).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Reiter disclosed the core architecture of the challenged claims: a flash memory system with a controller that performs logical-to-physical address translation. Reiter’s hierarchical scheme translated a Logical Block Address (LBA) into a superblock number, a block index, and a page index. Specifically, Reiter disclosed deriving a logical block number from an LBA via a division operation. The T10 Standards, particularly ZBC, disclosed a standard command set for zoned block storage devices, which are analogous to Reiter's superblocks. ZBC commands from a host included LBAs to specify read/write locations.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Reiter's flash memory architecture with the ZBC/SCSI command set to improve interoperability and provide a standardized way to manage the storage device. Petitioner contended that Reiter’s system did not specify a command set but supported widely used SCSI protocols. A POSITA would find it obvious to use the ZBC standard, as its "zones" are analogous to Reiter's "superblocks," both representing logical collections of blocks over a fixed LBA range.
    • Expectation of Success: A POSITA would have a reasonable expectation of success, as SCSI standards were designed for broad use across various storage devices, including flash memory. The logical constructs of ZBC's zoned block model could be readily layered on top of Reiter’s physical storage architecture.

Ground II: Obviousness over Reiter, T10 Standards, and Sinclair-367 - Claims 1, 13-14, and 19 are obvious over Reiter in view of ZBC, SBC-4, SPC-4, and Sinclair-367.

  • Prior Art Relied Upon: Reiter (Patent 8,301,861), T10 Standards, and Sinclair-367 (Application # 2005/0144367).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground I, adding Sinclair-367 to teach limitations related to wear-leveling, metadata management, and bad block handling. Petitioner asserted Sinclair-367 disclosed storing metadata, such as program/erase cycle counts, in each erase block to manage wear and improve lifespan. This addressed limitations in claims 13 and 14 regarding storing metadata on an independent basis and using it to trigger remapping operations. Sinclair-367 also taught remapping logical addresses from a defective block to a substitute block, which maps to the failure remapping steps of claim 1[e]. Further, Sinclair-367’s disclosure of organizing flash memory into multiple planes and using "metablocks" to perform simultaneous operations mapped to the concurrent write limitations of claim 19.
    • Motivation to Combine: A POSITA would be motivated to incorporate Sinclair-367's teachings to improve the reliability, longevity, and performance of the base Reiter/ZBC system. Since Reiter already contemplated bad block management, integrating Sinclair-367's more detailed methods for wear-leveling and data resiliency was presented as a predictable design choice. Similarly, incorporating multi-plane architecture for parallelism was a well-known technique to enhance throughput.

Ground IV: Obviousness over Ban, T10 Standards, Sinclair-367, and Yamada - Claims 1-14, 16, and 19-23 are obvious over Ban in view of ZBC, SBC-4, SPC-4, Sinclair-367, and Yamada.

  • Prior Art Relied Upon: Ban (Patent 5,404,485), T10 Standards, Sinclair-367 (Application # 2005/0144367), and Yamada (Application # 2011/0271032).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground substituted the foundational Reiter reference with Ban. Petitioner argued Ban disclosed an earlier flash memory system that emulated random access memory for compatibility with existing operating systems. Ban taught a two-step address translation, where a host address was decoded into a virtual address (comprising a block number and offset) which was then translated into a physical address. Critically, Ban disclosed that a logical unit/zone number could be derived from a logical address via a bit shift operation, which Petitioner equated to the "division operation" limitation of claim 1. The remaining references (T10, Sinclair-367, Yamada) were argued to provide the same features as in other grounds, such as standardized commands, bad block management, wear-leveling, and performance optimizations.
    • Motivation to Combine: The motivation was to take Ban’s foundational but older flash memory system and improve its compatibility, reliability, and performance using well-known, contemporary techniques. A POSITA would apply the widely used ZBC/SCSI command set to Ban’s device for interoperability. The reliability and performance enhancements from Sinclair-367 (bad block management, parallelism) and Yamada (performing maintenance during lulls in operation) were argued to be obvious improvements to any flash memory system, including Ban’s.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including Ground III (Reiter, ZBC, Sinclair-367, Yamada) and Ground V (Ban, ZBC, Sinclair-367, Yamada), which relied on similar motivations to combine references to add maintenance and wear-leveling functionalities.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-23 of the ’656 patent as unpatentable.