PTAB

IPR2025-01431

Samsung Electronics Co Ltd v. Netlist Inc

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Module with Switching Circuit
  • Brief Description: The ’731 patent discloses a memory module with a circuit that selectively couples one or more ports to memory devices. The circuit includes a "correction circuit" with a programmable impedance matching element designed to reduce signal noise, reflections, and impedance mismatches to improve signal integrity.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ellsberry and Dour - Claims 1-18 are obvious over Ellsberry in view of Dour.

  • Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and Dour (Patent 7,020,818).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ellsberry discloses a memory module with the core structural elements of claim 1, including a printed circuit board, multiple ranks of memory devices, and a circuit (a "Switch ASIC") coupled between the connector and memory devices. Ellsberry’s Switch ASIC acts as a correction circuit by using signal drivers to reduce loading and amplify signals. However, Ellsberry’s impedance control is limited. Petitioner contended that Dour remedies this deficiency by teaching a programmable on-die termination (ODT) circuit that serves as the claimed "programmable impedance matching circuit." Dour’s ODT circuit can be dynamically altered to properly terminate signals and prevent reflections, thereby maximizing data transfer rates.
    • Motivation to Combine: Petitioner asserted that a person of ordinary skill in the art (POSITA) would combine Dour’s programmable ODT with Ellsberry’s memory module architecture to improve signal integrity for higher-speed memory operations. As memory standards advanced toward faster data rates (e.g., DDR2, DDR3), more accurate signal termination became critical. A POSITA would have recognized the benefit of implementing Dour's advanced, programmable termination within Ellsberry’s Switch ASICs to handle the faster signals, reduce reflections, and compensate for environmental and physical variations (e.g., process, voltage, temperature) that Dour explicitly addresses.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because implementing termination functionalities within an ASIC on a memory module was a well-known design practice. Both references address the same field of high-speed memory signaling, and Dour provides detailed teachings on how to implement its programmable ODT circuit.

Ground 2: Obviousness over Ellsberry, Dour, and Abadeer - Claims 1-18 are obvious over the combination of Ellsberry and Dour in view of Abadeer.

  • Prior Art Relied Upon: Ellsberry (Application # 2006/0277355), Dour (Patent 7,020,818), and Abadeer (Application # 2008/0218290).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination of Ellsberry and Dour, arguing that Abadeer provides a further, well-known improvement. Petitioner asserted that Abadeer teaches an "automatic impedance matcher" that electronically senses the frequency of an incoming signal and automatically provides the appropriate matching capacitance. This functionality directly addresses the problem of voltage overshoots and undershoots that degrade signal integrity in high-frequency (GHz) systems, such as the memory modules at issue. Adding Abadeer's teachings would provide a "self-adjusting damper circuit" as recited in dependent claim 4.
    • Motivation to Combine: Petitioner argued that a POSITA would be motivated to incorporate Abadeer's teachings into the Ellsberry/Dour module to further enhance performance and reliability, particularly as the module operates at different high frequencies. While Dour taught dynamic adjustment based on PVT conditions, Abadeer taught automatic adjustment based on signal frequency. This would allow the module to optimize impedance matching without external tuning or training, ensuring robust signal integrity across the wide range of data rates used by DDR2/3 SDRAMs. The motivation was to maximize power transfer, minimize reflections, and prevent signal degradation at the highest operating speeds.
    • Expectation of Success: A POSITA would expect success in this combination because Abadeer provided detailed guidance for implementing its automatic impedance matcher. Integrating such functionality into Ellsberry’s Switch ASIC was a conventional design choice for improving the interface with memory devices, and Abadeer disclosed implementations that operated in the relevant frequency range of memory devices at the time.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-18 of the ’731 patent as unpatentable.