PTAB

IPR2025-01431

Samsung Electronics Co., Ltd. v. Netlist, Inc.

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1. Case Identification

2. Patent Overview

  • Title: Memory Module with Switching Circuit for Improved Signal Integrity
  • Brief Description: The ’731 patent describes a memory module with a circuit that selectively couples ports to memory devices. The circuit includes "correction circuits," such as programmable impedance matching circuits, to reduce signal noise and reflection, thereby improving signal integrity for high-speed data transmission between a memory controller and memory devices.

3. Grounds for Unpatentability

Ground 1: Claims 1-18 are obvious over Ellsberry in view of Dour.

  • Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and Dour (Patent 7,020,818).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ellsberry discloses a memory module architecture with memory devices arranged in multiple ranks (called "banks") and "Switch ASICs" that function as correction circuits by reducing resistive and capacitive loading on the data bus. Ellsberry’s Switch ASICs route data between a DIMM interface and the different memory ranks. Dour teaches a programmable on-die termination (ODT) circuit to properly terminate signals, prevent reflections, and maximize data transfer rates. Petitioner asserted that implementing Dour's programmable impedance matching circuit within Ellsberry’s Switch ASICs would render the key limitations of claim 1 obvious. For example, the "programmable impedance matching circuit" of claim 1 is taught by Dour's programmable ODT, and the "dynamic control" based on rank selection is met by adjusting Dour's ODT based on which of Ellsberry's memory banks is selected for communication, as different signal paths would have different electrical characteristics.
    • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would combine these references to improve signal integrity and support higher data rates, a well-known objective in memory system design. Ellsberry's architecture already isolates the memory devices from the host via Switch ASICs and includes basic impedance-related functions (e.g., a "squelch function" for ODT commands). A POSITA would have been motivated to incorporate Dour's more advanced, programmable ODT functionality directly into Ellsberry’s Switch ASICs to better manage signal termination for the different data paths associated with each memory rank, a known challenge at higher speeds.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because implementing impedance matching functionalities in ASICs on memory modules was a standard practice. Dour provides detailed teachings on its programmable ODT circuit, and Ellsberry’s Switch ASIC provides the logical location for this known type of signal integrity improvement.

Ground 2: Claims 1-18 are obvious over Ellsberry and Dour in view of Abadeer.

  • Prior Art Relied Upon: Ellsberry (Application # 2006/0277355), Dour (Patent 7,020,818), and Abadeer (Application # 2008/0218290).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the Ellsberry/Dour combination by adding the teachings of Abadeer. Abadeer discloses an "automatic impedance matcher" that electronically senses the frequency of an incoming signal and automatically provides the appropriate matching to minimize reflections and prevent voltage overshoot and undershoot, particularly in high-frequency (GHz range) applications. Petitioner argued that incorporating Abadeer’s automatic, frequency-aware matching functionality into the correction circuits of the Ellsberry/Dour module would have been an obvious improvement. This addition addresses dependent claims, such as claim 4's "self-adjusting damper circuits," by providing an automatic, self-calibrating termination solution.
    • Motivation to Combine: The primary motivation was to further enhance signal integrity for memory modules operating at very high and variable frequencies, such as those using DDR2 and DDR3 SDRAMs as contemplated by Ellsberry. Abadeer’s automatic matcher solves the problem of matching impedance across different operating frequencies without requiring external training or fine-tuning. A POSITA would have sought to integrate this automatic functionality into the Ellsberry/Dour design to create a more robust, high-performance memory module that could reliably operate across a wide speed range.
    • Expectation of Success: Success was expected because Abadeer’s teachings are directed to the same technical field of high-frequency signaling and could be readily implemented in the Switch ASICs of the primary combination. Abadeer provides detailed disclosure on implementing its automatic impedance matcher, making its integration into the existing design straightforward for a POSITA.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-18 of the ’731 patent as unpatentable.