PTAB

IPR2025-01444

Taiwan Semiconductor Mfg Co Ltd v. North America Intellectual Property Corp

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method for Reducing Charging Damage to Integrated Circuits During Semiconductor Manufacturing
  • Brief Description: The ’584 patent describes a method for manufacturing integrated circuits that reduces damage from stray electrical currents during plasma processing. The method involves creating a "dummy, non-interconnect opening" at the same time as a functional interconnect opening, which serves as an alternative shunt pathway to divert harmful charge away from sensitive device structures.

3. Grounds for Unpatentability

Ground 1: Obviousness of Claims 1 and 3-5 over Matsunaga

  • Prior Art Relied Upon: Matsunaga (JP Publication No. 11-74523A).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Matsunaga discloses all limitations of independent claim 1. Matsunaga teaches a method for manufacturing MOS transistors that explicitly aims to prevent charging damage during plasma processes. It describes simultaneously forming a functional "connecting hole 62" and a "dummy connecting hole 64" in a dielectric layer using a single Reactive Ion Etching (RIE) process. Petitioner contended that Matsunaga’s dummy hole functions identically to the one claimed in the ’584 patent, providing a shunt path for electric charges to the semiconductor substrate to reduce the potential difference at the gate and prevent damage. Dependent claims 3-5 were also argued to be taught by Matsunaga, as it discloses using a photoresist mask (claim 3) and forming a damascene opening (claim 4) that serves as a contact hole (claim 5).
    • Motivation to Combine (for §103 grounds): Not applicable for a single-reference ground. Petitioner asserted Matsunaga alone renders the claims obvious.
    • Expectation of Success (for §103 grounds): Not applicable for a single-reference ground.

Ground 2: Obviousness of Claim 2 over Matsunaga in view of Jaso

  • Prior Art Relied Upon: Matsunaga (JP Publication No. 11-74523A) and Jaso (Patent 6,093,631).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed dependent claim 2, which requires the exposed surface area of the interconnect and dummy openings to be higher than 5% of the die area. Petitioner argued that while Matsunaga teaches the fundamental process of creating dummy openings, Jaso provides the specific density requirements. Jaso addresses a well-known problem in semiconductor manufacturing—non-planar surfaces caused by "dishing" during Chemical Mechanical Polishing (CMP), a process utilized in Matsunaga. To solve this, Jaso teaches creating a uniform distribution of metal features, including dummy patterns, to achieve a "pattern factor" (metal area vs. total area) typically between 20-90%.
    • Motivation to Combine (for §103 grounds): A POSITA implementing Matsunaga's process would encounter the known problem of CMP dishing. A POSITA would combine Jaso's teachings to solve this predictable problem by patterning the interconnect and dummy openings to meet Jaso's recommended pattern densities, which far exceed the 5% threshold of claim 2.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success because the combination applies a known solution (Jaso's pattern density rules) to address a known problem (CMP dishing) in the same field of art.

Ground 3: Obviousness of Claims 1 and 3-6 over Eriguchi, Quirk, and Wolf

  • Prior Art Relied Upon: Eriguchi (Application # 2005/0006707), Quirk ("Semiconductor Manufacturing Technology," a 2001 textbook), and Wolf ("Silicon Processing for the VLSI Era," a 2002 textbook).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner presented this combination as a distinct alternative to the Matsunaga-based grounds. Eriguchi was argued to teach the core invention: a method to suppress plasma charging damage by simultaneously forming functional and dummy conductors in a dual damascene process. Eriguchi’s dummy conductor connects to the substrate to provide a shunt path. Quirk was cited for the well-known, fundamental concept of manufacturing a plurality of identical integrated circuit dies on a single silicon wafer, separated by scribe lanes for later dicing. Wolf was presented as a textbook reference providing standard implementation details for dual damascene processing (omitted by Eriguchi), such as using a photoresist mask to etch trenches and vias.
    • Motivation to Combine (for §103 grounds): A POSITA would combine these references to manufacture Eriguchi’s device on a commercial scale. It would be obvious to use the standard wafer-level fabrication techniques described in Quirk (multiple dies on a wafer) and the conventional dual damascene process steps detailed in Wolf (e.g., photoresist masking) to implement the charge-suppression method taught by Eriguchi.
    • Expectation of Success (for §103 grounds): Success would be predictable, as the combination merely involves applying standard, textbook manufacturing principles (Quirk and Wolf) to a specific device design (Eriguchi) that was intended for such fabrication.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including claims 1 and 3-5 over Matsunaga and Wolf; claim 6 over Matsunaga and Appel; claim 2 over Matsunaga, Wolf, and Jaso; and claim 6 over Matsunaga, Wolf, and Appel. These grounds relied on similar rationales, using references like Wolf and Appel to supply well-known implementation details for dual damascene processing and MOS gate formation, respectively.

4. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 1-6 of the ’584 patent as unpatentable.