PTAB

IPR2025-01559

Micron Semiconductor Products Inc v. Palisade Technologies LLP

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Non-Volatile Semiconductor Memory and Method of Formation
  • Brief Description: The ’974 patent relates to forming non-volatile semiconductor memories, specifically addressing challenges in manufacturing closely spaced conductive lines such as bit lines. It discloses using a sidewall assisted patterning process to create trenches with alternating profiles to mitigate issues like capacitive coupling.

3. Grounds for Unpatentability

Ground 1: Obviousness over Matsuno - Claims 1-2, 4, 12, and 15 are obvious over Matsuno.

  • Prior Art Relied Upon: Matsuno (Patent 8,592,978).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Matsuno, which discloses a method of fabricating a NAND flash memory device, teaches all limitations of independent claims 1 and 12. Matsuno discloses a semiconductor substrate with a dielectric layer into which first and second trenches are etched. Petitioner asserted Matsuno's first trenches have a tapered, trapezoidal shape, while its second trenches have substantially vertical sidewalls, resulting in a rectangular shape. This satisfies the limitation of two different trench shapes. These trenches are arranged in an alternating pattern and filled with conductive material to form alternating bit lines (BL1 and BL2), which Petitioner mapped to the claimed bit lines in the first trenches and additional bit lines in the second trenches.
    • Motivation to Combine: Not applicable for this single-reference ground.
    • Expectation of Success: Not applicable for this single-reference ground.
    • Key Aspects: The core of this ground is that a single prior art reference discloses all elements of the challenged claims, rendering them obvious to a person of ordinary skill in the art (POSITA) under 35 U.S.C. §103.

Ground 2: Obviousness over Matsuno in view of Zhang - Claims 6, 11, and 16 are obvious over Matsuno in view of Zhang.

  • Prior Art Relied Upon: Matsuno (Patent 8,592,978) and Zhang (Application # 2015/0162277).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Zhang teaches forming air gaps in trenches to reduce capacitance (claim 6) and creating trenches of different depths (claim 11), which are not explicitly disclosed in Matsuno. Zhang describes capping recesses in a dielectric layer to form air gaps and etching one set of trenches deeper than another to reach underlying contacts. Petitioner contended these known techniques could be applied to Matsuno’s structure. For claim 16, Petitioner argued that the process of depositing a metal layer to form the air gap caps, as taught by Zhang, would satisfy the claim limitation when applied to Matsuno's method.
    • Motivation to Combine: A POSITA would combine Matsuno with Zhang to solve the well-known problem of increasing inter-bit line capacitance as memory device density increases. Zhang's explicit teaching of incorporating air gaps provides a known solution to reduce capacitance and would have been seen as a predictable improvement to Matsuno's memory device. Similarly, varying trench depth is a known technique to manage electrical connections and capacitance.
    • Expectation of Success: A POSITA would have an expectation of success because both references use conventional semiconductor fabrication techniques (e.g., deposition, photolithography, etching). Combining them would involve applying a known technique (air gap formation) to a known device structure (Matsuno's NAND memory) to achieve a predictable result (reduced capacitance).

Ground 3: Obviousness over Kwak - Claims 1-2, 4, 11-12, and 15 are obvious over Kwak.

  • Prior Art Relied Upon: Kwak (Application # 2011/0032763).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Kwak, which is directed to a NAND flash memory device, discloses all elements of the independent claims. Kwak describes forming "even bit lines" and "odd bit lines" in an alternating pattern using different fabrication methods. Petitioner argued that the even bit lines, formed in a self-aligned manner between spacers, result in a first trench shape (e.g., curved or trapezoidal), while the odd bit lines, formed via a separate patterning process, result in a second, different trench shape (e.g., rectangular). This structure was alleged to meet the limitations of first and second trenches with different shapes arranged in an alternating pattern. Kwak's disclosure of different widths for even and odd bit lines was argued to meet the limitations of claim 4.
    • Motivation to Combine: Not applicable for this single-reference ground.
    • Expectation of Success: Not applicable for this single-reference ground.
  • Additional Grounds: Petitioner asserted additional obviousness challenges based on Matsuno in view of Kao (Patent 6,500,765), Kwak in view of Zhang, and Kwak in view of Kao, which relied on similar rationales for combining known semiconductor processing techniques to achieve predictable results.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-2, 4, 6, and 11-18 of Patent 9,524,974 as unpatentable.