PTAB

IPR2026-00011

NVIDIA Corp v. Onesta IP LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multi-Chip Graphics Processing
  • Brief Description: The ’803 patent discloses a system for improving graphics processing unit (GPU) performance by using multiple smaller processing units, called “chiplets,” instead of a single large monolithic chip. The system comprises a CPU communicably coupled to a GPU chiplet array, where the GPU chiplets are connected by a “passive crosslink” that is dedicated to inter-chiplet communications.

3. Grounds for Unpatentability

Ground I: Claims 1-4, 7, and 10 are obvious over Kelleher and Collins.

  • Prior Art Relied Upon: Kelleher (Patent 7,598,958) and Collins (Patent 11,610,862).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kelleher disclosed the fundamental architecture of the challenged claims. Kelleher taught a multi-chip GPU system with a “master” GPU chip and a “slave” GPU chip (meeting the ’803 patent’s definition of “chiplets”) that are packaged together and communicably coupled to a CPU via a bus. However, Kelleher’s interconnect was not the claimed “passive crosslink dedicated for inter-chiplet communications.” Petitioner asserted that Collins filled this gap by teaching a passive interconnect structure, an “embedded multi-die interconnect bridge” (EMIB), that is free of other signaling pathways and thus is dedicated to coupling chiplets. The combination of Kelleher’s GPU architecture with Collins’s passive interconnect allegedly rendered claim 1 obvious. Dependent claims were also argued to be obvious, as Collins taught a passive interposer (claim 2), PHY regions for I/O (claim 3), and conductive pillars for coupling to a circuit board (claim 10).
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would have been motivated to replace Kelleher’s interconnect with the EMIB taught by Collins to solve known performance limitations. Kelleher’s edge-to-edge chip configuration limited bandwidth. A POSITA would have recognized that Collins’s EMIB provided a well-known solution for creating a high-bandwidth, low-latency interconnect, thereby improving the performance of Kelleher’s system without requiring additional components or significant redesign.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because combining Collins’s well-understood passive interconnect technology with Kelleher’s known chiplet architecture was a predictable design choice involving the application of known techniques to achieve expected improvements in performance and efficiency.

Ground II: Claims 8 and 9 are obvious over Kelleher, Collins, Koker, and Sista.

  • Prior Art Relied Upon: Kelleher (Patent 7,598,958), Collins (Patent 11,610,862), Koker (Patent 10,909,652), and Sista (Application # 2009/0037658).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the Kelleher/Collins combination from Ground I to address the cache hierarchy limitations of claims 8 and 9. Petitioner argued that Koker disclosed a GPU architecture with multi-core groups (MCGs), each containing a local first-level cache memory hierarchy (L1 cache/shared memory) and access to a shared second-level (L2) cache. Sista further taught a “distributed shared cache architecture” where caches on separate dies (chiplets) form a single last-level cache (LLC) that is coherent across the system. Petitioner contended that adding Koker’s and Sista’s cache teachings to the Kelleher/Collins multi-chiplet GPU system would result in the cache hierarchy recited in claims 8 and 9, including a first cache hierarchy at a first GPU chiplet and a second, coherent cache hierarchy at a second GPU chiplet.
    • Motivation to Combine: The motivation was to improve the performance and efficiency of the base Kelleher/Collins system. A POSITA would have understood that implementing a sophisticated, multi-level cache hierarchy is a standard method for reducing latency and improving data sharing in multi-core or multi-chiplet processors. A POSITA would have looked to teachings like Koker and Sista for established techniques to implement an effective and coherent cache system, which would have been a predictable step to enhance the performance of the underlying chiplet-based GPU.
    • Expectation of Success: Petitioner asserted a high expectation of success, as implementing cache coherency protocols and memory hierarchies was a routine and well-understood practice in processor design. The combination involved applying known cache architecture principles from Koker and Sista to the multi-chiplet system of Kelleher/Collins, which was a predictable integration of complementary technologies.

4. Key Claim Construction Positions

  • “Chiplet”: Petitioner noted that the parties and the ITC Staff agreed to construe this term based on the ’803 patent’s explicit definition, which requires, among other things, that multiple active silicon dies are packaged as a monolithic unit and that the programming model preserves the concept of a single monolithic unit.
  • “Dedicated for inter-chiplet communications”: Petitioner argued this term should be construed as “used for transmission of only chiplet-to-chiplet signals.” This construction was central to the argument that Collins’s EMIB, which is free of other power and I/O routing, was necessary to render the claims obvious, as it satisfied the “dedicated” limitation in a way Kelleher’s interconnect did not.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4 and 7-10 of the ’803 patent as unpatentable.