PTAB

IPR2026-00017

Samsung Electronics Co Ltd v. Netlist Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Module with Distributed Data Buffers
  • Brief Description: The ’035 patent discloses a memory module, such as a DDR SDRAM DIMM, featuring a central module control device and multiple data buffers distributed horizontally across the module. This architecture is designed to manage timing discrepancies in signals that arise from the "fly-by" topology used in modern memory systems, where command and clock signals arrive at different memory devices at different times.

3. Grounds for Unpatentability

Ground 1: Claims 2-9 and 14-20 are obvious over Osanai, Butt, and Tokuhiro.

  • Prior Art Relied Upon: Osanai (Application # 2010/0312925), Butt (Application # 2007/0008791), and Tokuhiro (Patent 8,020,022).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Osanai taught the foundational architecture of the ’035 patent, including a memory module with a central command/address/control register buffer (module control device) and multiple distributed data register buffers. The combination with Tokuhiro taught using a write operation to measure fly-by delays and then applying that timing information to adjust subsequent read operations. The further combination with Butt taught a read/write training routine during initialization to optimize the alignment of data (DQ) and strobe (DQS) signals, which is necessary for reliable operation but not detailed in Osanai or Tokuhiro.
    • Motivation to Combine: A POSITA would combine these references to create a more robust and efficient memory system.
      • Osanai + Butt: A POSITA would incorporate Butt’s explicit strobe signal alignment training into Osanai’s system to ensure reliable data read operations at high speeds, a feature Osanai lacked.
      • Combination + Tokuhiro: A POSITA would replace Osanai’s inefficient method of performing separate read and write leveling operations with Tokuhiro’s more efficient technique of calculating read delays based on delays measured during write operations. Tokuhiro also taught using simple delay circuits to manage large fly-by delays (greater than one clock cycle) on the module itself, avoiding the need for more complex and costly FIFO circuitry in the system memory controller.
    • Expectation of Success: A POSITA would have a high expectation of success, as the combination involved applying known techniques (strobe alignment, fly-by delay compensation) to improve a conventional memory module architecture (fly-by topology) using predictable electronic circuits.

Ground 2: Claims 2-9 and 14-20 are obvious over the combination of Ground 1 and Ellsberry.

  • Prior Art Relied Upon: Osanai, Butt, Tokuhiro, and Ellsberry (Application # 2006/0277355).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1 to address dependent claims requiring specific data widths (e.g., claims 5, 7, 17, 19). While the primary combination taught the overall system, Petitioner argued Ellsberry expressly disclosed memory modules with the same distributed buffer architecture using either 1-byte wide (x8) memory devices or pairs of 4-bit wide (x4) memory devices, consistent with JEDEC standards.
    • Motivation to Combine: A POSITA designing a memory module based on the teachings of Ground 1 would be motivated to use standardized memory device configurations for compatibility and performance. Ellsberry provided a clear blueprint for implementing the system with common x4 and x8 memory devices. This modification was presented as a predictable design choice to meet industry standards.
    • Expectation of Success: The integration would be straightforward, as it involved selecting standard, commercially available memory components that were known to be compatible with the type of buffer architecture described in the primary references.

Ground 3: Claims 2-9 and 14-20 are obvious over the combination of Ground 1 and Kim.

  • Prior Art Relied Upon: Osanai, Butt, Tokuhiro, and Kim (Patent 6,184,701).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed claim 9, which recited a receiver circuit with a metastability detection circuit. Petitioner contended that Kim recognized the known problem of metastability in high-speed digital circuits, where a signal can be in an indeterminate state, leading to errors. Kim taught a specific "metastability detection/prevention circuit 20" for incorporation into circuits like data input buffers.
    • Motivation to Combine: A POSITA would be motivated to incorporate Kim’s metastability detection circuit into the control signal inputs of Osanai’s data buffers. This would ensure the reliable capture of critical control signals, preventing system failure due to metastable states—a known issue in high-speed memory interfaces. The Board had previously agreed in a related case that a POSITA would be motivated to include Kim's functionality in a similar system.
    • Expectation of Success: A POSITA would have a high expectation of success in integrating Kim's well-understood circuit into Osanai's data buffer to solve a known and critical problem, as it represented a direct application of a known solution to a known problem.

4. Key Claim Construction Positions

  • Petitioner argued that no claim terms required express construction for the prior art to invalidate the claims.
  • However, Petitioner noted that in a prior IPR involving the ’035 patent (IPR2022-00236), the Board interpreted "memory write operation" narrowly to exclude "write leveling operations." Petitioner contended that its asserted grounds rendered the claims obvious even under this narrow construction, as the combination taught using a normal write operation (not a write leveling operation) during initialization to measure the timing intervals needed for subsequent read adjustments.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 2-9 and 14-20 of the ’035 patent as unpatentable.