PTAB

IPR2026-00058

Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
  • Brief Description: The ’822 patent discloses a semiconductor structure, such as a MOSFET, that uses a source/drain region with a non-uniform lattice parameter distribution. This graded structure allegedly improves performance by reducing defects that occur at the interface between the strained layer and the substrate.

3. Grounds for Unpatentability

Ground 1: Obviousness over Koontz and Sridhar - Claims 1-14 are obvious over Koontz, with claims 8, 10, and 14 further obvious in view of Sridhar.

  • Prior Art Relied Upon: Koontz (Application # 2006/0134873) and Sridhar (Application # 2005/0090082).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Koontz teaches all limitations of claims 1-7, 9, and 11-13. Koontz discloses a CMOS structure with PMOS and NMOS transistors in N-wells and P-wells, respectively, on a common substrate. Crucially, Koontz teaches using strained source/drain recess structures (e.g., SiGe for PMOS, SiC for NMOS) and explicitly states their composition "can vary in composition vertically." Although Koontz describes this variation in terms of the resulting strain profile in the channel, Petitioner contended a POSITA would directly understand this requires varying the lattice parameter of the strained layer itself. For claims 8, 10, and 14, which add a "metal silicide layer" on a "silicon layer," Petitioner asserted that Sridhar supplies this teaching. Sridhar addresses the problem of increased resistance when forming silicide directly on a strained layer and teaches capping the strained layer with a thin silicon layer before silicidation.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Koontz with Sridhar because Koontz discloses forming silicide regions via a "suitable silicidation process" without specifying the details. Sridhar provides an improved, suitable process that was known to solve a common problem (increased resistance) associated with strained silicon devices. The express motivation was to reduce source/drain contact resistance, a goal also identified by Koontz.
    • Expectation of Success (for §103 grounds): Sridhar's technique was presented as a "drop-in" solution compatible with existing semiconductor processes like those in Koontz, ensuring a high expectation of success.

Ground 2: Anticipation by Orlowski - Claims 1-4 are anticipated by Orlowski.

  • Prior Art Relied Upon: Orlowski (Patent 7,238,580).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Orlowski discloses every element of claims 1-4 in a single reference. Orlowski teaches a CMOS integrated circuit with PMOS and NMOS transistors formed in N-wells and P-wells. The transistors include "stress-inducing source/drain (SISD) structures" made of SiGe (for PMOS) which are explicitly "characterized by a composition gradient." Orlowski teaches that this gradient is designed so the lattice parameter of the strained layer gradually changes, becoming closer to that of the substrate near the bottom of the structure. This directly maps to the core limitation of claim 1, which requires the difference in lattice parameter between the strained layer and substrate to be smaller near the bottom of the opening. Orlowski further discloses the specific P-type/SiGe configuration of claims 3 and 4.

Ground 3: Obviousness over Samoilov, Murthy, and Sridhar - Claims 1-14 are obvious over Samoilov in view of Murthy, with claims 8, 10, and 14 further obvious in view of Sridhar.

  • Prior Art Relied Upon: Samoilov (Application # 2005/0079692), Murthy (Patent 7,195,985), and Sridhar (Application # 2005/0090082).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Samoilov teaches the fundamental NMOS and PMOS transistor structures with strained layers having a "graded elemental concentration" to create a non-uniform lattice parameter. However, Samoilov depicts these transistors on separate n-type and p-type substrates. Murthy was argued to supply the well-known twin-well substrate structure for implementing both transistor types on a single substrate, a standard CMOS configuration. The combination of Samoilov's transistor design with Murthy's substrate was alleged to render claims 1-7, 9, and 11-13 obvious. For claims 8, 10, and 14, Petitioner relied on the same combination with Sridhar to add the silicon capping layer before silicidation, using the same rationale as in Ground 1.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Samoilov and Murthy to realize the widely known benefits of CMOS technology (higher speed, lower power consumption) by integrating NMOS and PMOS devices on a single chip, for which Murthy’s twin-well structure was a standard and optimal solution. The motivation to further add Sridhar was to solve the known problem of high contact resistance in strained silicon devices, as Samoilov's disclosure of forming a silicide layer would have prompted a POSITA to seek out an optimized and beneficial method.
    • Expectation of Success (for §103 grounds): The combination involved applying well-understood transistor designs (Samoilov) to a standard, compatible substrate architecture (Murthy), which was a common and predictable engineering task for a POSITA.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-14 of the ’822 patent as unpatentable.