PTAB

PGR2024-00047

Phison Electronics Corp v. Vervain LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
  • Brief Description: The ’546 patent discloses a data storage system comprising both multi-level cell (MLC) and single-level cell (SLC) non-volatile memory. A controller manages the memory by performing data integrity tests after write operations and, upon failure, remapping the data to a different physical location to extend the system’s operational lifetime.

3. Grounds for Unpatentability

Ground 1: Claims 1-7 are invalid under 35 U.S.C. §112 for Lack of Written Description and Indefiniteness

  • Core Argument for this Ground: Petitioner asserted that the challenged claims fail to meet the requirements of §112(a) and §112(b).
    • Written Description (§112(a)): Petitioner argued that key claim terms like “memory space” and “memory element” are unsupported abstractions introduced late in prosecution, nearly seven years after the priority date. The specification is grounded in physical SLC and MLC NAND flash modules with specific structures (e.g., “individually erasable blocks”), yet the claims abstract away from this disclosure. Further, the limitation “mapping is performed as necessitated by the system to maximize lifetime” allegedly lacks any corresponding disclosure, failing to show the inventor possessed the claimed invention.
    • Indefiniteness (§112(b)): Petitioner contended that the same abstract terms (“memory space,” “memory element”) render the claims indefinite, as a person of ordinary skill in the art (POSITA) could not ascertain their scope with reasonable certainty. The term “controller” was argued to be an abstract, functionally-claimed element lacking supporting structure (physical or algorithmic) in the specification. Additionally, the functional language describing when a “data integrity test” is performed was asserted to be ambiguous, rendering the claim scope unclear.

Ground 2: Claims 1-7 are obvious under 35 U.S.C. §103 over Gavens in view of POSITA knowledge

  • Prior Art Relied Upon: Gavens (Patent 8,634,240), in view of the general knowledge of a POSITA and supported by references including Sutardja (Application # 2008/0140918), Lee (’794 patent), and Moshayedi (Application # 2009/0327591).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Gavens taught all key elements of the claimed system. Gavens, which relates to managing errors in NAND flash, disclosed a memory system with MLCs, where some blocks are partitioned and configured to operate in a more durable two-state or pseudo-SLC (“pSLC”) mode. Gavens disclosed a controller that performs post-write read checks to test data integrity and, upon detecting excessive errors, remaps the data from a higher-density portion to a lower-density, more robust portion (its pSLC partition). This process inherently manages and extends the memory's useful life.
    • Motivation to Combine: Petitioner contended a POSITA would find it obvious to modify Gavens’s system. Gavens used partitioned MLCs to create its pSLC region. It was well-known in the art, as shown by references like Lee and Sutardja, to use a dedicated, "real" SLC module alongside MLC modules to serve as a more robust storage tier for frequently written data or for remapping data from failing MLC blocks. A POSITA would combine the teachings by substituting Gavens’s pSLC partition with a discrete SLC module to achieve even greater endurance and performance benefits, a predictable and well-understood design trade-off.
    • Expectation of Success: A POSITA would have a high expectation of success because using hybrid SLC/MLC architectures to improve endurance was a conventional and established practice in NAND flash memory design prior to the patent’s priority date.

Additional Grounds: Petitioner asserted that claims 1-7 are directed to patent-ineligible subject matter under 35 U.S.C. §101. The core argument was that the claim term "memory space" is an abstract idea (a property of memory), and the remaining claim elements merely recited conventional computer functions without adding an inventive concept.

4. Key Claim Construction Positions

  • “MLC memory modules” / “SLC memory modules”: Petitioner argued these terms should be construed as physical NAND flash modules with specific, distinct hardware structures and circuitry. An “SLC memory module” would have circuitry for writing one logical page in one pass, while an “MLC memory module” would have circuitry for writing two logical pages into a single physical page of cells. This construction was presented as crucial for highlighting how the claims improperly abstract from the physical invention disclosed in the specification, which is rooted entirely in NAND flash technology.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv is not warranted. It asserted that the petition was filed expeditiously and the parallel district court proceeding is in a very early stage, with a claim construction hearing scheduled for December 2024 and jury selection not until December 2025. Petitioner contended that the Post-Grant Review (PGR) is a more appropriate and efficient forum to address the complex validity challenges across eight related patents asserted by the Patent Owner, and that the strong merits of the petition weigh heavily in favor of institution to promote patent quality.

6. Relief Requested

  • Petitioner requested the institution of a Post-Grant Review and the cancellation of claims 1-7 of the ’546 patent as unpatentable under 35 U.S.C. §§ 101, 112, and 103.