PTAB

PGR2025-00011

Phison Electronics Corp v. Vervain LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
  • Brief Description: The ’370 patent relates to a hybrid non-volatile memory system using both Multi-Level Cell (MLC) and Single-Level Cell (SLC) memory. A controller manages data storage by maintaining an address map, performing a data integrity test, and, upon failure of the test, remapping and transferring data from an MLC element to a more robust SLC element to enhance the system's operational lifetime.

3. Grounds for Unpatentability

Ground 1: Claims 1-18 Lack Written Description under 35 U.S.C. § 112(a)

  • Core Argument for this Ground: Petitioner argued that the ’370 patent specification fails to provide adequate written description for key claim limitations, rendering the claims invalid. The petition asserted that terms like "memory space" and "memory element" were abstract concepts introduced late in the patent family's prosecution and are unsupported by the specification, which consistently disclosed concrete hardware "modules" composed of erasable "blocks." Furthermore, Petitioner contended that independent claims 1 and 18 are inoperable because they nonsensically require the "transfer" of "stored data" that has just failed a data integrity test. Transferring known erroneous data to a more robust part of the memory system serves no useful purpose and contradicts the patent's stated goal of increasing reliability.

Ground 2: Claims 1-18 are obvious over Gavens in view of POSITA knowledge

  • Prior Art Relied Upon: Gavens (Patent 8,634,240) and its incorporated references, including Gorobets (Application # 2011/0153912), Paley (Application # 2010/0172180), and Chen (Patent 6,456,528), in view of the knowledge of a Person of Ordinary Skill in the Art (POSITA).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Gavens discloses a complete multi-modal NAND flash system that anticipates the core functionality of the ’370 patent. Gavens taught partitioning a standard MLC memory array into a high-density portion and a lower-density, higher-endurance "pseudo-SLC" (pSLC) portion. It further disclosed a post-write-read error management scheme where written data is compared against a cached "original copy" (a data integrity test). If the error rate in the MLC portion is too high, the system remaps the logical address and rewrites the original data to the more robust pSLC portion. Petitioner contended this directly maps to the challenged claims' system comprising an MLC space, an SLC space (Gavens' pSLC portion), a controller, an address map, and a data integrity test triggering a transfer to the more durable memory region.
    • Motivation to Combine: A POSITA would have found it obvious to substitute Gavens' pSLC partition with a discrete, "native" SLC memory module. This was a well-known design choice in the art to achieve similar or superior performance and endurance benefits. Using a dedicated SLC module was a predictable solution for creating a hybrid memory system, not an inventive step.
    • Expectation of Success: A POSITA would have had a high expectation of success in this substitution. The underlying Flash Translation Layer (FTL) and logical-to-physical mapping principles for managing hybrid memory were well understood, and NAND flash controllers were routinely designed to manage different memory types within a single system.

  • Additional Grounds: Petitioner also asserted that claims 1-12 are indefinite under 35 U.S.C. § 112(b) for failing to particularly point out the invention, citing abstract terms like "memory space," a lack of disclosed structure for the "controller" to perform its recited functions, and an improper mixing of system and method limitations in the claims.

4. Key Claim Construction Positions

  • "MLC/SLC memory space" and "memory element": Petitioner proposed that these terms should be construed based on the physical hardware disclosed in the specification and understood by a POSITA. "MLC memory" was defined as having circuitry capable of storing multiple logical pages per physical page, while "SLC memory" lacks this capability. The abstract "spaces" should be construed as the physical modules, and "elements" should be construed as the fundamental addressable units, such as physical pages.
  • "transfer": Petitioner argued the claimed "transfer" of failed "stored data" is nonsensical and inoperable. It asserted that a POSITA, seeking an operable construction from the specification's flowcharts, would understand "transfer" to mean the process of reading the correct "retained data" (the original data intended for writing) from a buffer and writing it to a newly remapped physical location in the SLC memory, rather than copying the corrupted data.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under the Fintiv factors would be inappropriate. The petition asserted that the parallel litigation in the Western District of Texas is in its early stages, with discovery just commencing and no substantive rulings on validity. The Markman hearing was postponed, indicating minimal investment by the court. Petitioner contended that Post-Grant Review (PGR) is a more efficient forum for resolving the complex validity issues across eight related patents that rely on the same specification but use different claim language, thereby serving the interests of system efficiency and patent quality.

6. Relief Requested

  • Petitioner requests institution of Post-Grant Review and cancellation of claims 1-18 of Patent 11,967,370 as unpatentable.