PTAB

PGR2026-00001

Samsung Semiconductor Inc v. Netlist Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Module with Power Management
  • Brief Description: The ’366 patent describes a memory system, such as a Dual In-line Memory Module (DIMM), that includes both volatile (e.g., DDR SDRAM) and non-volatile memory subsystems. The system features a controller and a backup power supply (e.g., capacitors or a battery) designed to save data from the volatile memory to the non-volatile memory upon detection of a power failure.

3. Grounds for Unpatentability

Ground 1: Claims 1-38 Lack Written Description under 35 U.S.C. § 112

  • Core Argument for this Ground: Petitioner argued that all claims of the ’366 patent lack written description because they recite a combination of limitations that is not disclosed in the specification. The core of the argument is that the claims improperly import features from the modern DDR5 memory standard, which was developed more than a decade after the patent’s priority date.
    • Petitioner asserted the claims require the independent operation of two separate groups of DDR SDRAM devices during "normal operation" (i.e., communication with the host computer). However, the specification allegedly only describes such independent control and "slicing" of memory in the context of slower, internal "backup/restore operations" that occur during a power failure, which are distinct from normal, high-speed host communication.
    • The petition contended that the specification does not provide support for key claimed features, such as enabling a first group of at least 40 data lines independently of a second group, resulting in a total of at least 72 data conduits, which mirrors the architecture of DDR5 memory modules (e.g., two 40-bit subchannels) but not the single 72-bit-wide channel disclosed in earlier standards relevant to the patent's timeframe.
    • Petitioner also argued that the negative limitation requiring components to receive power only via a set of four regulated voltage lines lacks written description. The specification allegedly teaches the opposite: during normal operation, components receive power from the main system input, and the regulated voltage lines from the conversion element are used for backup power during a power failure.

Ground 2: Claims 1-38 are obvious over Perego in view of Harris and Amidi

  • Prior Art Relied Upon: Perego (Patent 7,363,422), Harris (Application # 2006/0174140), and Amidi (Patent 7,724,604).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner alleged the combination of Perego, Harris, and Amidi teaches all limitations of the challenged claims.
      • Perego discloses a flexible memory module with a buffer device that supports different types and numbers of memory devices. Critically, Perego teaches a module with independent memory channels that can transfer information simultaneously (e.g., a 40-bit channel and a 32-bit channel), rendering obvious the claims’ DDR5-like multi-channel architecture.
      • Harris teaches an on-board voltage regulator module (VRM) for a DIMM that converts a single external power supply (e.g., +12V) into the multiple, appropriate local voltages required by different on-module components like DRAMs and buffer chips.
      • Amidi discloses a power management system for a memory module that monitors the main system voltage, detects power failures, and switches to an on-board battery backup to preserve data, including placing the DRAMs into a low-power self-refresh state.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references to solve known problems. A POSITA would first be motivated to implement Harris’s on-board VRM on Perego’s flexible memory module. Perego’s module is designed to use different types of memory, which require different operating voltages; Harris’s VRM provides a known, cost-effective solution for supplying these varied voltages locally on the module, enhancing its flexibility and upgradeability. A POSITA would then be further motivated to incorporate Amidi’s power monitoring and battery backup system into the Perego/Harris module to address the well-understood risk of losing critical data in volatile memory during a power failure.
    • Expectation of Success: Petitioner asserted a POSITA would have a reasonable expectation of success. The combination involves integrating known solutions for predictable purposes: using a standard VRM (Harris) to power a memory module (Perego) and adding a standard backup power circuit (Amidi) to enhance reliability. The use of buck converters for voltage regulation and self-refresh modes for data preservation were all well-known techniques.
    • Key Aspects: Petitioner noted that the Board had previously found motivation to combine Harris and Amidi in IPRs against related patents. The mapping for dependent claims (2-15, 17-28, 30-38) was addressed by showing the individual or combined teachings of the references met the additional limitations, such as using a FIFO buffer for staging data (taught by the prior art for efficient writes to non-volatile memory) and detecting over/under voltage conditions (taught by Amidi).

4. Relief Requested

  • Petitioner requests institution of Post Grant Review and cancellation of claims 1-38 of the ’366 patent as unpatentable.