US 10,186,523 B2
Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical gridGeneral
US 10,186,523 B2
Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid
Tech Center:
2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing
Examiner:
Robert G Bachner
Art Unit:
2898 Semiconductors/Memory
Agent:
Martine Penilla Group, LLP
Inventors:
Scott T. Becker; Michael C. Smayling
Assignee:
Priority:
03/09/06
Filed:
08/31/18
Granted:
01/22/19
Expiration:
02/27/23
Abstract
An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.
Cooperative Patent Classification (CPC)
H10H10D84/0186H10DH01L2924/0002H01LG06F30/392G06F