US 10,707,851 B1
DOUBLE DATA RATE CIRCUIT AND DATA GENERATION METHOD IMPLEMENTING PRECISE DUTY CYCLE CONTROLGeneral
US 10,707,851 B1
DOUBLE DATA RATE CIRCUIT AND DATA GENERATION METHOD IMPLEMENTING PRECISE DUTY CYCLE CONTROL
Tech Center:
2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing
Examiner:
Kenneth B Wells
Art Unit:
2842 Electrical Circuits and Systems
Agent:
Inventors:
Jae Hyeong Kim; Daesik Song
Priority:
05/05/19
Filed:
06/10/19
Granted:
07/07/20
Expiration:
05/05/39
Abstract
A double data rate circuit includes a clock generator, a clock divider and a multiplexer. The clock generator is used to receive a source clock signal to generate a pair of complementary clock signals. The clock divider is coupled to the clock generator, and used to generate four multiphase clock signals using only single-edge transitions of the pair of complementary clock signals. The four multiphase clock signals are successively out-of-phase by 90°. The multiplexer is coupled to the clock divider, and used to multiplex multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits upon a first edge transition of and a second edge transition of two of the four multiphase clock signals, respectively, and outputting each selected data bit as the output data stream.