US 5,890,195 A
Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sramGeneral
US 5,890,195 A
Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sram
Tech Center:
2100 Computer Architecture and Software
Examiner:
John W. Cabeca
Art Unit:
2139 Memory Access and Control
Inventors:
G. R. MOHAN RAO
Assignee:
Priority:
03/13/97
Filed:
05/14/97
Granted:
03/30/99
Expiration:
05/14/17
Abstract
A memory 601 comprising a plurality of static random access cell arrays 701, and a plurality of sets of latches 703 each for storing address bits associated with data stored in a corresponding one of the static random access cell arrays 701. Bit comparison circuitry 503 compares a received address bit with an address bit stored in each of the plurality of sets of latches 703 and enables access to a selected one of the static random cell arrays 701 corresponding to the set of latches 703 storing an address bit matching the received bit.