US 6,023,085 A
Core cell structure and corresponding process for NAND-type high performance flash memory deviceGeneral
US 6,023,085 A
Core cell structure and corresponding process for NAND-type high performance flash memory device
Tech Center:
2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing
Examiner:
Sheila V. Clark
Art Unit:
2815 Semiconductors/Memory
Agent:
Amin, Eschweiler & Turocy, LLP
Inventors:
HAO FANG
Assignee:
Priority:
12/18/97
Filed:
12/18/97
Granted:
02/08/00
Expiration:
12/18/17
Abstract
A method of forming a NAND-type flash memory device (200) includes forming a stacked gate flash memory structure (346) for one or more flash memory cells in a core region (305) and forming a transistor structure having a first gate oxide (336) and a gate conductor (338) for both a select gate transistor (344) in the core region (305) and a low voltage transistor (342) in a periphery region (328). In addition, a NAND-type flash memory device (200) includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (344) and a periphery region (328, 332) comprising a low voltage transistor (342) and a high voltage transistor (350), wherein a structure of the select gate transistor (344) and the low voltage transistor (342) are substantially the same.