Method for verifying and improving run-time of a memory test

A method of generating and verifying a memory test is disclosed. A simulator is used to verify that the sequence of time-ordered commands complies with a set of operating constraints for the memory. A packer may thereafter be used to optimize run time of the verified test.

INFORMATION STORAGE

Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation-External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor-Pattern generation

STATIC STORES 

Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation-Arrangements for designing test circuits, e.g. design for test [DFT] tools

Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation-External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor-Timing aspects, clock generation, synchronisation

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