US 6,813,742 B2
High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architectureGeneral
US 6,813,742 B2
High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture
Tech Center:
2100 Computer Architecture and Software
Examiner:
Albert Decady
Art Unit:
2133 Memory Access and Control
Inventors:
Quang Nguyen
Assignee:
Priority:
01/02/01
Filed:
01/02/01
Granted:
11/02/04
Expiration:
12/15/21
Abstract
A Bandband Processor for Wireless Communications is presented. The invention encompasses several improved Turbo codes method to provide a more practical and simpler method for implementation a Turbo Codes Decoder in ASIC or DSP coding. (1) A plurality of pipelined pipelined Log-MAP decoders are used for iterative decoding of received data. (2) In a pipeline mode, Decoder A decodes data from the De-interleaver RAM memory while the Decoder B decodes data from the De-interleaver RAM memory at the same time. (3) Log-MAP decoders are simpler to implement in ASIC with only Adder circuits, and are low-power consumption. (4) Pipelined Log-MAP decoders method provide high speed data throughput, one output per clock cycle.
Cooperative Patent Classification (CPC)
H03H03M13/3922H03MH04L1/0071H04L