US 7,195,341 B2
Power and ground buss layout for reduced substrate sizeGeneral
US 7,195,341 B2
Power and ground buss layout for reduced substrate size
Tech Center:
2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing
Examiner:
Juanita D. Stephens
Art Unit:
2853 Printing/Measuring and Testing
Inventors:
David G. King; Kristi M. Rowe
Assignee:
Priority:
09/30/04
Filed:
09/30/04
Granted:
03/27/07
Expiration:
06/18/25
Abstract
A semiconductor substrate for a micro-fluid ejection device. The substrate includes plurality of micro-fluid ejection actuators disposed adjacent a fluid supply slot in the semiconductor substrate. A plurality of power transistors, occupying a power transistor active area of the substrate, are disposed adjacent the ejection actuators and are connected through a first metal conductor layer to the ejection actuators. An array of logic circuits, occupying a logic circuit area of the substrate, is disposed adjacent the plurality of power transistors and is connected through a polysilicon conductor layer to the power transistors. A power conductor and a ground conductor for the ejection actuators is routed in a second metal conductor layer. The power conductor overlaps at least a portion of the power transistor active area of the substrate and the ground conductor overlaps at least a portion of the logic circuit area of the substrate.
Cooperative Patent Classification (CPC)
B41B41J2/04541B41J