US 7,199,052 B2
Seed layers for metallic interconnectsGeneral
US 7,199,052 B2
Seed layers for metallic interconnects
Tech Center:
2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing
Examiner:
Bradley K. Smith
Art Unit:
2891 Semiconductors/Memory
Agent:
COHEN, URI, DR.
Inventors:
Uri Cohen
Assignee:
COHEN, URI, DR.
Priority:
10/02/99
Filed:
02/14/05
Granted:
04/03/07
Expiration:
10/02/19
Abstract
One embodiment of the present invention is a method for making copper or a copper alloy interconnects, which method includes: (a) forming a patterned insulating layer over a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening; (b) depositing a barrier layer over the patterned insulating layer including over the field and inside surfaces of the at least one opening, the barrier layer consists of a refractory metal or an alloy of a refractory metal; (c) physical vapor depositing a substantially non-conformal seed layer consisting of copper or a copper alloy over the barrier layer, wherein said substantially non-conformal seed layer is thicker than about 500 Å over the field; (d) chemical vapor depositing a substantially conformal seed layer consisting of copper or a copper alloy over the substantially non-conformal seed layer; and (e) filling the at least one opening by electroplating a metallic layer consisting of copper or a copper alloy over the substantially conformal seed layer.
Cooperative Patent Classification (CPC)
H01H01L2221/1089H01L