US 7,282,445 B2
Multiple seed layers for interconnectsGeneral
US 7,282,445 B2
Multiple seed layers for interconnects
Tech Center:
2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing
Examiner:
Bradley K Smith
Art Unit:
2891 Semiconductors/Memory
Agent:
COHEN, URI, DR.
Inventors:
Uri Cohen
Assignee:
COHEN, URI, DR.
Priority:
10/02/99
Filed:
01/17/07
Granted:
10/16/07
Expiration:
10/02/19
Abstract
One embodiment of the present invention is a method for depositing two or more seed layers over a substrate, the substrate includes a patterned insulating layer which comprises at least one opening surrounded by a field, the at least one opening and the field being ready for depositing one or more seed layers, the at least one opening having sidewalls and bottom, and the method including: (a) providing a CVD chamber capable of depositing a conformal (i.e., continuous) seed layer over the sidewalls and bottom of the at least one opening; (b) providing a PVD chamber capable of depositing a PVD seed layer over the substrate; (c) configuring an automatic controller with recipe information, the recipe information including deposition sequence, process and timing parameters for operation of the CVD and the PVD chambers; (d) operating the automatic controller in accordance with the recipe information to cause the CVD chamber to deposit a conformal (i.e., continuous) first seed layer over the sidewalls and bottom of the at least one opening, the first seed layer having a thickness less than about 200 Å over the field; (e) operating the controller in accordance with the recipe information to cause the PVD chamber to deposit a second seed layer over the first seed layer, the second seed layer having a thickness greater than about 100 Å over the field; and (f) operating the controller in accordance with the recipe information to stop the deposition of the second seed layer prior to sealing the at least one opening, thereby leaving enough room for electroplating inside the at least one opening.
Cooperative Patent Classification (CPC)
H01H01L2221/1089H01L