US 7,378,702 B2
VERTICAL MEMORY DEVICE STRUCTURESGeneral
US 7,378,702 B2
VERTICAL MEMORY DEVICE STRUCTURES
Tech Center:
2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing
Examiner:
Andy Huynh
Art Unit:
2818 Semiconductors/Memory
Inventors:
Sang-Yun Lee
Assignee:
DAEHONG TECHNEW CORPORATION
Priority:
09/03/04
Filed:
09/03/04
Granted:
05/27/08
Expiration:
06/21/24
Abstract
Vertically oriented semiconductor memory cells are added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor memory cells are physically separated from each other, and are not disposed within the same semiconductor body. The plurality of vertically oriented semiconductor memory cells can be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures, which are then supplied with various dielectric coatings, gate electrodes, and contacts by means of further processing operations. Alternatively, the plurality of vertically oriented semiconductor memory cells may be completely fabricated prior to attachment. DRAMs, SRAMs, non-volatile memories, and combinations of memory types can be provided.
Cooperative Patent Classification (CPC)
H01H01L2924/01015H01LH10D88/00H10D