US 7,725,759 B2
System and method of managing clock speed in an electronic deviceGeneral
US 7,725,759 B2
System and method of managing clock speed in an electronic device
Tech Center:
2100 Computer Architecture and Software
Examiner:
Thomas Lee
Art Unit:
2116 Computer Error Control, Reliability, & Control Systems
Agent:
Inventors:
Matthew Henson
Assignee:
Priority:
06/29/05
Filed:
06/29/05
Granted:
05/25/10
Expiration:
04/20/26
Abstract
A method of controlling a clock frequency is disclosed and includes monitoring a plurality of master devices that are coupled to a bus within a system. The method also includes receiving an input from at least one of the plurality of master devices. The input can be a request an increase to the clock frequency of the bus. Further, the method includes selectively increasing the clock frequency of the bus in response to the request.
Cooperative Patent Classification (CPC)
Y02Y02D10/00Y02DG06F1/3203G06F