US 7,807,549 B2
Method for low temperature bonding and bonded structureGeneral
US 7,807,549 B2
Method for low temperature bonding and bonded structure
Tech Center:
2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing
Examiner:
N Drew Richards
Art Unit:
2895 Semiconductors/Memory
Inventors:
Qin-Yi Tong; Gaius Gillman Fountain; Paul M. Enquist
Assignee:
Priority:
02/16/00
Filed:
10/31/07
Granted:
10/05/10
Expiration:
11/07/22
Abstract
A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
Cooperative Patent Classification (CPC)
H01H01L2924/10253H01LY10T156/1043Y10S148/012Y10TH10D62/10H10D