US 8,020,014 B2
Method for power reduction and a device having power reduction capabilitiesGeneral
US 8,020,014 B2
Method for power reduction and a device having power reduction capabilities
Tech Center:
2100 Computer Architecture and Software
Examiner:
Suresh K Suryawanshi
Art Unit:
2115 Computer Error Control, Reliability, & Control Systems
Agent:
VLSI TECHNOLOGY LLC
Inventors:
Michael Priel; Dan Kuzmin; Anton Rozen; Leonid Smolyanski
Assignee:
Priority:
05/11/05
Filed:
05/11/05
Granted:
09/13/11
Expiration:
09/25/27
Abstract
A method for power reduction, the method includes determining whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively providing power to at least a portion of a component of an integrated circuit during a low power mode. A device having power reduction capabilities, the device includes power switching circuitry, and a power management circuitry adapted to determine whether to power down at least the portion of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power.
Cooperative Patent Classification (CPC)
G06G06F2212/1028G06FY02D10/00Y02D