US 8,443,216 B2
Hardware automatic performance state transitions in system on processor sleep and wake eventsGeneral
US 8,443,216 B2
Hardware automatic performance state transitions in system on processor sleep and wake events
Tech Center:
2100 Computer Architecture and Software
Examiner:
Stefan Stoynov
Art Unit:
2116 Computer Error Control, Reliability, & Control Systems
Inventors:
Josh P. de Cesare; Jung Wook Cho; Toshi Takayanagi; Timothy J. Millet
Assignee:
Priority:
04/07/10
Filed:
08/21/12
Granted:
05/14/13
Expiration:
04/07/30
Abstract
In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
Cooperative Patent Classification (CPC)
G06G06F1/3287G06FY02D30/50Y02D