US 8,549,339 B2
PROCESSOR CORE COMMUNICATION IN MULTI-CORE PROCESSORGeneral
US 8,549,339 B2
PROCESSOR CORE COMMUNICATION IN MULTI-CORE PROCESSOR
Tech Center:
2100 Computer Architecture and Software
Examiner:
Dennis M Butler
Art Unit:
2115 Computer Error Control, Reliability, & Control Systems
Agent:
Inventors:
Andrew WOLFE; Marc Elliot LEVITT
Assignee:
Priority:
02/26/10
Filed:
02/26/10
Granted:
10/01/13
Expiration:
08/04/31
Abstract
Embodiments of the disclosure generally set forth techniques for handling communication between processor cores. Some example multi-core processors include a first set of processor cores in a first region of the multi-core processor configured to dynamically receive a first supply voltage and a first clock signal, a second set of processor cores in a second region of the multi-core processor configured to dynamically receive a second supply voltage and a second clock signal, and an interface block coupled to the first set of processor cores and the second set of processor cores, wherein the interface block is configured to facilitate communications between the first set of processor cores and the second set of processor cores.
Cooperative Patent Classification (CPC)
Y02Y02D10/00Y02DG06F9/5094G06F