US 8,593,888 B2
SEMICONDUCTOR MEMORY DEVICEGeneral
US 8,593,888 B2
SEMICONDUCTOR MEMORY DEVICE
Tech Center:
2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing
Examiner:
Huan Hoang
Art Unit:
2827 Semiconductors/Memory
Inventors:
Reiji MOCHIDA; Takafumi Maruyama; Yukimasa Hamamoto
Assignee:
Priority:
12/21/10
Filed:
08/22/12
Granted:
11/26/13
Expiration:
12/21/30
Abstract
In a semiconductor memory device, the output of a regulator is coupled to the inputs of first and second switches, the output of the first switch is coupled to a path for supplying the drain voltage of a memory cell in the first mode, and the output of the second switch is coupled to a path for supplying the gate voltage of the memory cell in the second mode. A fourth switch is placed in parallel with the second switch: the output of the fourth switch is coupled to the output of the second switch, to supply the gate voltage of the memory cell in the first mode. Thus, one regulator is used as both the regulator for the drain voltage of the memory cell and the regulator for the gate voltage of the memory cell.
Cooperative Patent Classification (CPC)
G11G11C16/10G11C