US 8,884,373 B2 | SEMICONDUCTOR DEVICE

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US 8,884,373 B2

SEMICONDUCTOR DEVICE

Tech Center:

2800 Semiconductors/Memory, Circuits/Measuring and Testing, Optics/Photocopying, Printing/Measuring and Testing

Examiner:

Fernando L Toledo

Art Unit:

2897 Semiconductors/Memory

Agent:

McDermott Will & Emery LLP

Inventors:

Yoshihiro SATO; Hideyuki ARAI; Takayuki YAMADA

Assignee:

NUVOTON TECHNOLOGY CORPORATION JAPAN

Priority:

11/04/11

Filed:

10/31/12

Granted:

11/11/14

Expiration:

11/09/31

Abstract

A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

Cooperative Patent Classification (CPC)

H10H10D84/0177H10DH01L21/823842H01LY10S257/903Y10S

H10

Semiconductor devices; electric solid-state devices not otherwise provided for

H10D

Inorganic electric semiconductor devices

H10D84/0177

Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on si wafers or on gaas-on-si wafers-manufacture or treatment-integrating together multiple components covered by h10d12/00 or h10d30/00, e.g. integrating multiple igbts-the components including insulated gates, e.g. igfets-the components including complementary igfets, e.g. cmos devices-manufacturing their gate conductors-the gate conductors having different materials or different implants

H10D84/038

Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on si wafers or on gaas-on-si wafers-manufacture or treatment-characterised by using material-based technologies-using group iv technology, e.g. silicon technology or silicon-carbide [sic] technology-using silicon technology, e.g. sige

H01

Electric elements

H01L

Semiconductor devices not covered by class h10

H01L21/823842

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof-manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof -manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate -with subsequent division of the substrate into plural individual devices -to produce devices, e.g. integrated circuits, each consisting of a plurality of components-the substrate being a semiconductor, using silicon technology -field-effect technology-mis technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type-complementary field-effect transistors, e.g. cmos-with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes-gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

H01L21/76895

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof-manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof -manufacture of specific parts of devices defined in group h01l21/70 -applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics-characterised by the formation and the after-treatment of the conductors -local interconnects; local pads, as exemplified by patent document ep0896365

H01L21/28518

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof-manufacture or treatment of semiconductor devices or of parts thereof-the devices having potential barriers, e.g. a pn junction, depletion layer or carrier concentration layer-the devices having semiconductor bodies comprising elements of group iv of the periodic table or aiiibv compounds with or without impurities, e.g. doping materials -manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups h01l21/20 - h01l21/268-deposition of conductive or insulating materials for electrodes ; conducting electric current-from a gas or vapour, e.g. condensation-of conductive layers-on semiconductor bodies comprising elements of group iv of the periodic table-the conductive layers comprising silicides

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