US 9,606,907 B2
Memory module with distributed data buffers and method of operationGeneral
US 9,606,907 B2
Memory module with distributed data buffers and method of operation
Tech Center:
2100 Computer Architecture and Software
Examiner:
Edward Dudek, Jr.
Art Unit:
2136 Memory Access and Control
Agent:
Jamie J. Zheng, Esq.
Inventors:
Hyun Lee; Jayesh R. Bhakta
Assignee:
Priority:
07/16/09
Filed:
08/20/13
Granted:
03/28/17
Expiration:
05/05/25
Abstract
A memory module is operable to communicate with a memory controller via a data bus and a control/address bus and comprises a module board; a plurality of memory devices mounted on the module board; and multiple sets of data pins along an edge of the module board. Each respective set of the multiple sets of data pins is operatively coupled to a respective set of multiple sets of data lines in the data bus. The memory module further comprises a control circuit configured to receive control/address information from the memory controller via the control/address bus and to produce module control signals. The memory module further comprises a plurality of buffer circuits each being disposed proximate to and electrically coupled to a respective set of the multiple sets of data pins. Each buffer circuit is configured to respond to the module control signals by enabling data communication between the memory controller and at least one first memory device among the plurality of memory devices and by isolating at least one second memory device among the plurality of memory devices from the memory controller.
Cooperative Patent Classification (CPC)
G11G11C5/066G11CG06F12/00G06F