DCT

8:17-cv-01030

Netlist Inc v. SK Hynix Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 8:17-cv-01030, C.D. Cal., 06/14/2017
  • Venue Allegations: Venue is alleged to be proper in the Central District of California because Defendants have regular and established places of business in the district and have committed alleged acts of infringement there. Plaintiff is also headquartered within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s DDR4 LRDIMM and RDIMM server memory modules infringe two patents related to high-performance memory module architecture and operational handshaking protocols.
  • Technical Context: The technology relates to high-performance Dual In-Line Memory Modules (DIMMs), which are critical components for servers used in cloud computing, virtualization, and high-performance computing (HPC) markets.
  • Key Procedural History: The complaint alleges a history of failed licensing negotiations initiated by Netlist in 2015 under the JEDEC standards body’s patent policy. It also references prior litigation and an ITC investigation filed in 2016 by Netlist against SK hynix involving the parent patents of those asserted in this suit, alleging this history establishes pre-suit knowledge. Notably, subsequent to the filing of this complaint, inter partes review (IPR) proceedings were initiated against both patents-in-suit. Those proceedings ultimately resulted in the U.S. Patent and Trademark Office cancelling all claims of both the '907 and '623 patents.

Case Timeline

Date Event
2009-06-12 ’623 Patent Priority Date
2010-04-15 ’907 Patent Priority Date
2015-01-01 Netlist allegedly contacted Hynix regarding patent portfolio license
2016-01-01 Hynix allegedly became aware of parent patents to those in-suit
2016-06-01 Netlist allegedly sent Hynix a formal license offer
2017-01-03 U.S. Patent No. 9,535,623 Issued
2017-03-28 U.S. Patent No. 9,606,907 Issued
2017-06-14 Complaint Filed
2017-12-14 IPR filed against the ’623 Patent (No. IPR2018-00303)
2017-12-22 IPRs filed against the ’907 Patent (No. IPR2018-00362, -00363)
2021-07-13 All claims of ’623 Patent cancelled via IPR Certificate
2021-08-17 All claims of ’907 Patent cancelled via IPR Certificate

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,606,907 - “Memory module with distributed data buffers and method of operation,” Issued March 28, 2017

The Invention Explained

  • Problem Addressed: The patent addresses the challenge that increasing the number of memory chips (DRAMs) on a memory module to achieve higher capacity also increases the electrical load on the data bus, which can degrade performance and limit operational speed (’907 Patent, col. 2:5-11).
  • The Patented Solution: The invention proposes using multiple "data transmission circuits" (or buffers) that are distributed across the memory module's printed circuit board (PCB), positioned close to the memory chips they control (’907 Patent, col. 8:1-34). These circuits selectively connect only the active memory chips to the system memory controller at any given time, effectively isolating the electrical load of the inactive chips and allowing the module to support higher density and speed (’907 Patent, Abstract).
  • Technical Importance: This architecture enables the design of high-capacity, high-speed memory modules, such as Load-Reduced DIMMs (LRDIMMs), that are essential for data-intensive applications in modern servers and data centers (Compl. ¶¶ 9-10).

Key Claims at a Glance

  • The complaint asserts independent claims 1, 16, 30, 43, and 58 (Compl. ¶ 19).
  • Independent claim 1 includes the following essential elements:
    • A memory module with a defined data width and structure.
    • A module control circuit that produces control signals.
    • A plurality of memory devices, divided into at least a first and second set.
    • M "buffer circuits" that are configured to respond to the control signals.
    • The buffer circuits allow data communication with the first set of memory devices while isolating the electrical load of the second set.
    • The buffer circuits are physically mounted and distributed on the PCB between the memory devices and the edge connector.
  • The complaint also asserts numerous dependent claims and reserves the right to assert others (Compl. ¶ 19).

U.S. Patent No. 9,535,623 - “Memory module capable of handshaking with a memory controller of a host system,” Issued January 3, 2017

The Invention Explained

  • Problem Addressed: When a memory module performs its own internal initialization or "training" sequences, the main system memory controller needs to know when the task is complete. The conventional method of repeatedly checking a status register ("polling") is inefficient and wastes system resources, delaying the overall boot process (’623 Patent, col. 4:31-48).
  • The Patented Solution: The patent describes a dual-mode handshaking system using an existing pin on the memory module, such as the "error-out" pin. In a first, normal operational mode, the pin functions as specified by industry standards to report parity errors. However, in a second, initialization mode, the same pin is repurposed to send a "notification signal" to the memory controller, indicating the status of the internal training sequence. This creates an efficient, interrupt-based notification without requiring new hardware pins (’623 Patent, Abstract; col. 9:1-15).
  • Technical Importance: This method improves the efficiency of system initialization, which can reduce boot times for servers with complex, high-capacity memory configurations (Compl. ¶¶ 10-11).

Key Claims at a Glance

  • The complaint asserts independent claims 1, 12, and 21 (Compl. ¶ 30).
  • Independent claim 1 includes the following essential elements:
    • A memory module with a module controller having an "open drain output."
    • The controller generates a "parity error signal" and drives it via the open drain output when in a "first mode."
    • The controller causes the module to enter a "second mode" in response to a command.
    • The controller generates a "notification signal" indicating the status of a training sequence and drives it via the same open drain output when in the "second mode."
    • A PCB with an "error edge connection" is coupled to the open drain output for communication.
  • The complaint asserts a number of dependent claims and reserves the right to assert others (Compl. ¶ 30).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are SK hynix’s DDR4 LRDIMM (Load-Reduced Dual In-Line Memory Modules) and DDR4 RDIMM (Registered Dual In-Line Memory Modules) (Compl. ¶¶ 19, 30). The '907 patent is asserted against LRDIMMs, and the '623 patent is asserted against both LRDIMMs and RDIMMs (Compl. ¶¶ 19, 30).

Functionality and Market Context

The complaint alleges these are high-performance memory modules designed for the server, cloud computing, virtualization, and HPC markets (Compl. ¶ 9). It states that the accused products comply with industry standards set by JEDEC (Joint Electron Device Engineering Council) (Compl. ¶ 12). The LRDIMM products, in particular, incorporate a memory buffer to manage electrical load, a feature central to the '907 patent’s technology (Compl. ¶ 11). The complaint further alleges that both LRDIMM and RDIMM products perform internal initialization routines, which forms the basis for infringement allegations under the '623 patent (Compl. ¶ 33). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits (Exhibits 3 and 5) that were not included with the filed document; therefore, the infringement theories are summarized below in prose.

'907 Patent Infringement Allegations

The complaint’s narrative theory of infringement alleges that SK hynix’s DDR4 LRDIMM products meet the limitations of the asserted claims because their architecture embodies the core invention (Compl. ¶ 19). The complaint contends that the memory buffer components on the accused LRDIMMs function as the claimed "buffer circuits," which selectively connect certain memory devices to the system controller while isolating the electrical load of others (Compl. ¶¶ 10, 19). This functionality is alleged to improve performance in a manner that infringes the patent. The complaint identifies an exemplary accused product (part number HMA84GL7AMR4N-TF TE AB) and references a Hynix Q1 2017 Databook as containing evidence of the infringing functionality (Compl. ¶¶ 14, 20).

Identified Points of Contention ('907 Patent)

  • Scope Questions: A primary issue may be whether the term "buffer circuit," as defined and used in the patent, can be construed to read on the memory buffers used in SK hynix’s JEDEC-standard LRDIMMs. The dispute may focus on whether the accused buffers perform the specific load-isolation and switching functions in the manner required by the claims.
  • Technical Questions: A key factual question is how the buffers in the accused products are physically and electrically implemented. Evidence regarding their placement ("distributed" and "proximate" to memory devices) and their precise effect on electrical load will be central to determining infringement.

'623 Patent Infringement Allegations

The complaint alleges that SK hynix’s DDR4 LRDIMM and RDIMM products infringe the '623 patent by implementing the claimed "handshaking" method (Compl. ¶ 30). The theory is that during their initialization phase, the accused modules repurpose a specific I/O pin—which operates as an error-reporting pin during normal operation—to send a "notification signal" to the host system to indicate the status of an internal training sequence (Compl. ¶ 29; '623 Patent, Abstract). This alleged dual-mode signaling functionality is the foundation of the infringement claim (Compl. ¶¶ 30, 33).

Identified Points of Contention ('623 Patent)

  • Scope Questions: A likely point of contention is the construction of "notification signal." The court may need to determine if any status-related signal sent by the accused modules during startup qualifies, or if the term is limited to a signal with the specific purpose of triggering a system interrupt to exit a "wait state" as described in the patent’s background ('623 Patent, col. 4:31-48).
  • Technical Questions: The core evidentiary question is whether a pin on the accused modules is, in fact, used for two different functions depending on the operational mode (initialization vs. normal operation). Answering this question may require detailed technical analysis of the products' hardware, firmware, and signaling protocols.

V. Key Claim Terms for Construction

'907 Patent: “buffer circuit” (claim 1)

  • Context and Importance: This term is the central element of the invention. Whether the memory buffer on SK hynix's standard-compliant LRDIMM infringes will depend almost entirely on the construction of this term.
  • Intrinsic Evidence for a Broader Interpretation: The patent abstract describes the invention broadly as a "plurality of buffer circuits each being disposed proximate to and electrically coupled to a respective set of the multiple sets of data pins" that enables communication while isolating other devices, which may support a functional definition (’907 Patent, Abstract).
  • Intrinsic Evidence for a Narrower Interpretation: The specification includes detailed figures, such as Figure 5, illustrating a specific logic-gate implementation of the buffer circuit (’907 Patent, Fig. 5, col. 15:56-16:55). This could support an argument that the term should be limited to the specific structures disclosed or their equivalents, rather than any component that performs a general buffering function.

'623 Patent: “notification signal” (claim 1)

  • Context and Importance: The existence of a "notification signal" is a prerequisite for infringement. The dispute will likely center on whether the signals used by the accused modules during initialization meet the claimed definition.
  • Intrinsic Evidence for a Broader Interpretation: The claim language defines the signal by its function: "indicating at least one status of one or more training sequences" (’623 Patent, col. 16:39-42). This suggests any signal conveying such status could infringe.
  • Intrinsic Evidence for a Narrower Interpretation: The detailed description frames the invention as a solution to the inefficiency of "polling" and describes a system where the signal can trigger an interrupt to abort a CPU "wait" state (’623 Patent, col. 4:26-59). This may support a narrower construction requiring the signal to be part of an interrupt-driven, non-polling handshaking mechanism.

VI. Other Allegations

Indirect Infringement

The complaint alleges both induced and contributory infringement for both patents. The inducement claims are based on allegations that SK hynix provides datasheets and instruction manuals that encourage and instruct end-users on the infringing use of the products (Compl. ¶¶ 23, 34). The contributory infringement claims are based on the allegation that the accused LRDIMM and RDIMM products have no substantial non-infringing use and are a material part of the patented inventions (Compl. ¶¶ 24, 34).

Willful Infringement

Willfulness is alleged for both patents, based on purported pre-suit knowledge (Compl. ¶¶ 25, 35). The complaint asserts that SK hynix was aware of the parent patents ('185 and '837) since at least January 2016 through prior litigation and licensing negotiations, and that this knowledge of the shared technology and specifications put SK hynix on notice of infringement by the asserted child patents ('907 and '623) (Compl. ¶¶ 21, 32).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. A question of patent validity: The most critical issue in this case arises from post-filing events. With all asserted claims of both the '907 and '623 patents having been cancelled in inter partes review proceedings, the fundamental question is whether a viable case for infringement remains, pending the outcome of any appeals of those administrative decisions.

  2. A question of scope vs. standards: Should the patents survive any appeal, a central issue will be the conflict between the patent claims and the JEDEC industry standards the accused products allegedly follow. The court would need to resolve whether the patents claim a specific, proprietary implementation or a broader functionality that is practiced by standard-compliant LRDIMM and RDIMM modules.

  3. A question of dual-mode functionality: For the '623 patent, a key evidentiary hurdle would be demonstrating that a pin on the accused SK hynix modules performs the specific dual-role required by the claims—serving as a standard parity error output in one mode and as a "notification signal" for initialization status in another.