DCT

3:18-cv-02848

Intel Corp v. Tela Innovations Inc

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:18-cv-02848, N.D. Cal., 03/15/2019
  • Venue Allegations: Venue is based on Defendant Tela Innovations, Inc. having its principal place of business in the Northern District of California.
  • Core Dispute: Plaintiff Intel seeks a declaratory judgment of non-infringement and unenforceability for ten patents owned by Defendant Tela related to gridded semiconductor layout methodologies.
  • Technical Context: The technology concerns structured, grid-based layouts for semiconductor features, a design-for-manufacturing technique intended to improve yield and performance predictability for integrated circuits at advanced process nodes.
  • Key Procedural History: The complaint details a complex history, alleging that: (1) a 2007 Covenant Not to Sue (CNTS) between the parties bars assertion of most patents-in-suit; (2) Tela is taking positions inconsistent with those it took in a 2013 ITC action where Intel was a third party; (3) Tela’s founders misappropriated the core patented technology from a university professor, who is a true inventor; and (4) Tela committed inequitable conduct by improperly claiming early priority dates to which the patents are not entitled, allegedly to avoid prior art and the terms of the CNTS.

Case Timeline

Date Event
2006-03-09 Tela files U.S. Provisional Application No. 60/781,288, the purported priority document for all Patents-in-Suit
2007-05-09 Intel and Tela enter into a Covenant Not To Sue (CNTS)
2007-11-XX Intel's 45nm Penryn product becomes commercially available
2008-11-04 U.S. Patent No. 7,446,352 issues
2011-05-17 U.S. Patent No. 7,943,966 issues
2011-05-24 U.S. Patent No. 7,948,012 issues
2011-10-04 U.S. Patent No. 8,030,689 issues
2012-04-XX Intel releases its 22nm products
2012-09-04 U.S. Patent No. 8,258,552 issues
2014-07-XX Intel releases its 14nm products
2016-08-23 U.S. Patent No. 9,425,272 issues
2016-09-13 U.S. Patent No. 9,443,947 issues
2018-11-27 U.S. Patent No. 10,141,334 issues
2018-11-27 U.S. Patent No. 10,141,335 issues
2019-01-22 U.S. Patent No. 10,186,523 issues
2019-03-15 Intel files Second Amended Complaint for Declaratory Judgment

II. Technology and Patent(s)-in-Suit Analysis

No probative visual evidence provided in complaint.

U.S. Patent No. 7,943,966, “Integrated Circuit And Associated Layout With Gate Electrode Level Portion Including At Least Two Complimentary Transistor Forming Linear Conductive Segments And At Least One Non-Gate Linear Conductive Segment,” issued May 17, 2011

The Invention Explained

  • Problem Addressed: As semiconductor manufacturing processes attempt to create features smaller than the wavelength of light used for photolithography, unpredictable light interactions between arbitrarily shaped, neighboring features can distort the final circuit, causing device failures and reducing yield (’966 Patent, col. 1:17-40).
  • The Patented Solution: The invention proposes a "dynamic array architecture" that restricts circuit layouts to primarily linear, parallel shapes in any given layer above the diffusion layer (’966 Patent, col. 2:1-24). This regularity makes the light interactions predictable and allows for constructive interference to reinforce the desired shapes, reducing the need for complex optical corrections and improving manufacturability (’966 Patent, col. 1:53-67).
  • Technical Importance: This "gridded" or "1D" layout approach represented a method for improving design-for-manufacturing (DFM) to counteract the increasing unpredictability of photolithography at sub-wavelength feature sizes (Compl. ¶75).

Key Claims at a Glance

  • The complaint identifies independent claims 1 and 2 as being asserted (Compl. ¶79).
  • Independent Claim 1 (abridged): A semiconductor device layout comprising:
    • a diffusion level layout portion;
    • a gate electrode level layout portion including a plurality of linear-shaped layout features placed to extend lengthwise in a first direction so as to extend parallel to each other;
    • wherein at least two of the linear-shaped layout features form gate electrodes of at least two complimentary transistors; and
    • wherein at least one of the linear-shaped layout features is a non-gate linear conductive segment.
  • Independent Claim 2 (abridged): An integrated circuit device comprising:
    • a substrate region;
    • a gate electrode level region including a plurality of linear conductive segments formed to have their lengths extend in a first direction in a parallel manner;
    • wherein at least two of the linear conductive segments are active linear conductive segments forming gate electrodes of at least two complimentary transistors; and
    • wherein at least one of the linear conductive segments is a non-gate linear conductive segment.

U.S. Patent No. 7,948,012, “Semiconductor Device Having 1965 NM Gate Electrode Level Region Including At Least Four Active Linear Conductive Segments And At Least One Non-Gate Linear Conductive Segment,” issued May 24, 2011

The Invention Explained

  • Problem Addressed: The patent addresses the same photolithography challenges as the ’966 Patent: unpredictable light interactions from complex, two-dimensional feature layouts reducing manufacturing yield for advanced semiconductors (’012 Patent, col. 1:21-44).
  • The Patented Solution: The patent describes a "dynamic array architecture" where conductive features in the gate electrode level are restricted to parallel, linear shapes (’012 Patent, col. 2:5-29). This structured topology is intended to make lithographic effects predictable and use constructive light interference to improve feature printing, thereby enhancing manufacturability (’012 Patent, col. 2:1-17).
  • Technical Importance: As described for the ’966 Patent, this approach sought to impose layout regularity to manage the growing complexity of sub-wavelength semiconductor manufacturing (Compl. ¶75).

Key Claims at a Glance

  • The complaint identifies independent claims 1 and 2 as being asserted (Compl. ¶85).
  • Independent Claim 1 (abridged): A semiconductor device layout comprising:
    • a diffusion level layout portion;
    • a gate electrode level layout portion including a plurality of linear-shaped layout features placed to extend lengthwise in a first direction so as to extend parallel to each other;
    • wherein at least four of the linear-shaped layout features are active linear conductive segments that form gate electrodes of transistors; and
    • wherein at least one of the linear-shaped layout features is a non-gate linear conductive segment.
  • Independent Claim 2 (abridged): An integrated circuit device comprising:
    • a substrate region;
    • a gate electrode level region including a plurality of linear conductive segments formed to have their lengths extend in a first direction in a parallel manner;
    • wherein at least four of the linear conductive segments are active linear conductive segments that form gate electrodes of transistors; and
    • wherein at least one of the linear conductive segments is a non-gate linear conductive segment.

Multi-Patent Capsule: U.S. Patent No. 8,030,689

  • Patent Identification: U.S. Patent No. 8,030,689, “Integrated Circuit Device And Associated Layout Including Separated Diffusion Regions Of Different Type Each Having Four Gate Electrodes With Each Of Two Complementary Gate Electrode Pairs Formed From Respective Linear Conductive Segment,” issued October 4, 2011 (Compl. ¶13).
  • Technology Synopsis: This patent describes a semiconductor device with separated P-type and N-type diffusion regions. The layout includes linear conductive segments forming complementary gate electrode pairs for transistors in these regions, consistent with the gridded layout architecture of the family.
  • Asserted Claims: Independent claims 1 and 2 (Compl. ¶91).
  • Accused Features: Intel's 22nm and 14nm products are accused of using the claimed technology (Compl. ¶91).

Multi-Patent Capsule: U.S. Patent No. 8,258,552

  • Patent Identification: U.S. Patent No. 8,258,552, “Semiconductor Device Including At Least Six Transistor Forming Linear Shapes With At Least Two Transistor Forming Linear Shapes Having Offset Ends,” issued September 4, 2012 (Compl. ¶14).
  • Technology Synopsis: This patent claims a semiconductor device with at least six linear shapes forming transistors in a gate layer region. A key feature is that some of these linear shapes have offset ends, a specific geometric arrangement within the broader gridded layout theme.
  • Asserted Claims: Independent claims 1, 48, and 49 (Compl. ¶96).
  • Accused Features: Intel's 22nm and 14nm products are accused of using the claimed technology (Compl. ¶96).

Multi-Patent Capsule: U.S. Patent No. 9,425,272

  • Patent Identification: U.S. Patent No. 9,425,272, “Semiconductor Chip Including Integrated Circuit Including Four Transistors Of First Transistor Type And Four Transistors Of Second Transistor Type With Electrical Connections Between Various Transistors And Methods For Manufacturing The Same,” issued August 23, 2016 (Compl. ¶15).
  • Technology Synopsis: This patent focuses on a chip with specific numbers of two different transistor types and their electrical connections. A key limitation is that the edges of the conductive structures are "substantially straight," reinforcing the theme of linear, regular layouts. This patent is central to Intel's inequitable conduct allegations regarding the improper addition of new matter (Compl. ¶124).
  • Asserted Claims: Independent claims 1 and 29 (Compl. ¶101).
  • Accused Features: Intel's 22nm and 14nm products are accused of using the claimed technology (Compl. ¶101).

Multi-Patent Capsule: U.S. Patent No. 9,443,947

  • Patent Identification: U.S. Patent No. 9,443,947, “Semiconductor Chip Including Region Having Integrated Circuit Transistor Gate Electrodes Formed By Various Conductive Structure Of Specified Shape And Position And Method For Manufacturing The Same,” issued September 13, 2016 (Compl. ¶16).
  • Technology Synopsis: Similar to the '272 Patent, this patent claims a semiconductor chip with conductive transistor gate electrodes having "substantially straight" edges. This patent is also a subject of Intel's inequitable conduct allegations (Compl. ¶151).
  • Asserted Claims: Independent claims 1 and 29 (Compl. ¶106).
  • Accused Features: Intel's 22nm and 14nm products are accused of using the claimed technology (Compl. ¶106).

Multi-Patent Capsule: U.S. Patent No. 7,446,352

  • Patent Identification: U.S. Patent No. 7,446,352, “Dynamic Array Architecture,” issued November 4, 2008 (Compl. ¶17).
  • Technology Synopsis: This patent is an early patent in the family, describing the core "Dynamic Array Architecture." It claims linear gate electrode tracks and linear conductor tracks that extend in a single common direction, establishing the fundamental "one-dimensional" layout concept.
  • Asserted Claims: The complaint does not specify which claims of the '352 Patent are asserted, but notes it is one of the Patents-in-Suit (Compl. ¶45, 175).
  • Accused Features: Intel's products are accused of using the claimed technology (Compl. ¶45).

Multi-Patent Capsule: U.S. Patent No. 10,141,334 & U.S. Patent No. 10,141,335

  • Patent Identification: U.S. Patent No. 10,141,334 and U.S. Patent No. 10,141,335, both titled “Semiconductor Chip Including Region Having Rectangular-Shaped Gate Structures And First-Metal Structures,” issued November 27, 2018 (Compl. ¶18, 19).
  • Technology Synopsis: These recent patents claim chips with rectangular-shaped gate and first-metal structures positioned on horizontal and vertical grids, respectively. They include specific dimensional limitations (e.g., gate pitch ≤ 193 nm, width ≤ 45 nm) that are central to Intel's allegations that Tela added new matter to its applications to capture Intel's commercial products (Compl. ¶152, 153).
  • Asserted Claims: The complaint does not specify which claims are asserted but notes Tela has asserted them against Intel (Compl. ¶56, 111).
  • Accused Features: Intel products are accused of infringement (Compl. ¶56).

Multi-Patent Capsule: U.S. Patent No. 10,186,523

  • Patent Identification: U.S. Patent No. 10,186,523, “Semiconductor Chip Having Region Including Gate Electrode Features Formed In Part From Rectangular Layout Shapes On Gate Horizontal Grid And First-Metal Structures Formed In Part From Rectangular Layout Shapes On At Least Eight First-Metal Gridlines Of First-Metal Vertical Grid,” issued January 22, 2019 (Compl. ¶20).
  • Technology Synopsis: This patent, issued shortly before the complaint was filed, also describes a chip with rectangular gate and metal structures on a grid system. Tela asserted this patent in the ITC action and amended its counterclaims in this case to include it (Compl. ¶56).
  • Asserted Claims: The complaint does not specify which claims are asserted.
  • Accused Features: Intel products are accused of infringement (Compl. ¶56).

III. The Accused Instrumentality

  • Product Identification: Intel's products manufactured using at least its 22nm, 14nm, and 10nm process nodes, including its FinFET-based products (Compl. ¶47, 79).
  • Functionality and Market Context:
    • The accused instrumentalities are cutting-edge microprocessors and related chips that form the basis of high-performance computers (Compl. ¶25). The relevant technology is the "gridded" layout methodology used to fabricate these chips, which involves placing semiconductor features in a grid-like pattern (Compl. ¶26).
    • A central allegation in the complaint is that the accused 22nm, 14nm, and 10nm products use the same "two-dimensional conductive structures in the gate layer" as Intel's older 45nm products (Compl. ¶80, 86). Intel alleges that in a prior ITC action, Tela distinguished these 45nm products as non-infringing because Tela's patents required strictly "one-dimensional" structures (Compl. ¶42).

IV. Analysis of Infringement Allegations

The complaint is for declaratory judgment of non-infringement and does not contain claim charts mapping patent claims to accused products. Instead, it presents a narrative theory of non-infringement. The primary non-infringement argument is that Tela is estopped from asserting infringement against Intel’s current products because Tela allegedly took the position in a prior ITC action that Intel’s technologically similar 45nm products did not infringe.

  • Identified Points of Contention:
    • Scope Questions: A central issue will be the construction of terms like "linear-shaped layout features" (’966 Patent) and "linear conductive segments" (’012 Patent). The dispute raises the question of whether these terms, which Intel characterizes as requiring "one-dimensional" structures, can be construed to cover the "two-dimensional conductive structures" that Intel alleges are used in its accused products (Compl. ¶42, 80).
    • Legal Questions: A key legal question is whether Tela will be precluded by judicial or prosecution history estoppel from asserting an infringement theory that is allegedly inconsistent with arguments it made to distinguish Intel's 45nm products in the 2013 ITC Action (Compl. ¶42, 80, 86).

V. Key Claim Terms for Construction

  • The Term: "linear-shaped layout features" (from claim 1 of the ’966 Patent) and "linear conductive segments" (from claim 2 of the ’012 Patent).
  • Context and Importance: The definition of "linear" is critical to Intel's primary non-infringement defense. Practitioners may focus on this term because Intel's core argument is that its products use "two-dimensional" structures, which it alleges Tela previously argued were distinct from the claimed "one-dimensional" or "linear" structures (Compl. ¶42, 80). The case may turn on whether the accused structures fall within the scope of this term.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification of the ’966 Patent states that the layout features are "substantially rectangular" (’966 Patent, Abstract) and that a "consistent vertical cross-section shape" defines a linear feature (’966 Patent, col. 2:1-5). A party could argue this language does not preclude a linear segment from being part of a larger grid or having minor variations.
    • Evidence for a Narrower Interpretation: The background of the ’966 Patent contrasts the invention with prior art that allowed "essentially any two-dimensional topology" and "bends that wrap around each other" (’966 Patent, col. 1:26-30). The patent repeatedly emphasizes that features in layers above diffusion extend in "only a first parallel direction" (’966 Patent, col. 2:1-13). Figures such as Fig. 5 in the ’966 patent depict exclusively straight, parallel lines in the gate electrode layer, which may support a narrower construction limited to strictly one-dimensional features.

VI. Other Allegations

  • Indirect Infringement: The complaint does not allege indirect infringement; it seeks a declaratory judgment of non-infringement.
  • Willful Infringement: The complaint does not allege willful infringement. Instead, it makes extensive allegations regarding Tela's alleged bad faith in asserting its patents (Compl. ¶2).
  • Inequitable Conduct and Unenforceability: Intel alleges the '272, '947, '334, and '335 patents are unenforceable due to inequitable conduct (Compl. Count VII). The complaint alleges that Tela knowingly added new subject matter (e.g., specific width and pitch limitations like "less than 45 nanometers") to later patent applications to capture Intel's products, but improperly filed them as "continuations" rather than "continuations-in-part" to claim an unentitled priority date of March 9, 2006 (Compl. ¶123-127, 133-136). This was allegedly done to avoid Intel's own 22nm and 14nm products, which were publicly available before the new matter was added, from being considered invalidating prior art (Compl. ¶138).
  • Inventorship and Standing: Intel alleges the core technology of the Patents-in-Suit was misappropriated from Professor Lawrence Pileggi and that he is a true co-inventor (Compl. Count XII). Because Professor Pileggi has not assigned his rights to Tela, Intel argues Tela lacks standing to assert the patents (Compl. Count XV). Further, Intel alleges it has secured a license to the patents from Professor Pileggi, providing another basis for non-infringement (Compl. Count XIV).

VII. Analyst’s Conclusion: Key Questions for the Case

This declaratory judgment action extends far beyond a typical infringement dispute, focusing primarily on questions of patent enforceability and ownership. The outcome will likely depend on the resolution of several threshold, non-technical issues.

  • A core issue will be one of inventorship and title: can Intel prove its allegations that Tela’s named inventors misappropriated the core technology from Professor Pileggi? A finding for Intel on this issue could invalidate the patents or confirm that Tela lacks sole standing to bring suit.
  • A second key issue will be one of prosecution integrity and priority: did Tela engage in inequitable conduct by adding new matter to its patent applications while improperly claiming a 2006 priority date? The resolution of this question will determine the correct priority date for several patents, which in turn dictates the universe of applicable prior art and whether the patents are barred from assertion against Intel by the 2007 Covenant Not to Sue.
  • A third dispositive question will be one of estoppel and claim scope: is Tela bound by its alleged prior statements distinguishing "one-dimensional" patented layouts from Intel's "two-dimensional" product layouts? This will frame the technical non-infringement analysis and may preclude Tela from advancing its current infringement theories.