DCT

3:18-cv-03502

Samsung Semiconductor Inc v. BiTMICRO LLC

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:18-cv-03502, N.D. Cal., 06/12/2018
  • Venue Allegations: Venue is asserted based on Defendant BiTMICRO Networks, Inc. being a California corporation with its principal place of business in the district, and on BiTMICRO's patent enforcement activities targeting companies with a principal place of business in the district, including Samsung Semiconductor, Inc.
  • Core Dispute: Plaintiff Samsung seeks a declaratory judgment that its solid-state drives and other semiconductor products do not infringe four patents owned by Defendant BiTMICRO related to memory system architecture and operation.
  • Technical Context: The patents relate to methods for improving the performance and density of solid-state storage devices, a critical technology for consumer electronics, enterprise computing, and data centers.
  • Key Procedural History: This declaratory judgment action was filed in response to an ongoing U.S. International Trade Commission (ITC) investigation, Inv. No. 337-TA-1097, which BiTMICRO initiated against Samsung. An ITC Administrative Law Judge issued an Initial Determination finding that BiTMICRO satisfied the domestic industry requirement for three of the four patents-in-suit ('416, '103, '243) but failed to do so for the '190 Patent, which was terminated from the investigation.

Case Timeline

Date Event
2000-11-30 '416 Patent Priority Date
2003-03-04 '416 Patent Issue Date
2005-12-29 '243 and '103 Patents Priority Date
2009-09-04 '190 Patent Priority Date
2010-11-02 '243 Patent Issue Date
2012-01-10 '103 Patent Issue Date
2015-09-15 '190 Patent Issue Date
2017-12-21 BiTMICRO files ITC Complaint against Samsung
2018-01-08 BiTMICRO files Amended ITC Complaint
2018-01-26 ITC institutes Investigation 337-TA-1097
2018-05-11 ITC issues Initial Determination on Domestic Industry
2018-06-12 Samsung files Complaint for Declaratory Judgment

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,529,416 - Parallel Erase Operations in Memory Systems

Issued March 4, 2003 ('416 Patent)

The Invention Explained

  • Problem Addressed: The patent describes that flash memory write operations must be preceded by an erase operation, which is significantly slower than read or write operations and creates a performance bottleneck for the entire memory system ('416 Patent, col. 1:59-65, col. 2:30-32).
  • The Patented Solution: The invention proposes a method to mitigate this bottleneck by identifying multiple blocks of data in a cache that need to be written to different flash memory chips, issuing the slow erase commands to those chips in a rapid sequence so they execute in parallel, and then sequentially issuing the faster write commands to the now-erased locations ('416 Patent, col. 7:1-6, col. 9:26-34; Fig. 7). This parallelization of the erase step is intended to substantially reduce the cumulative time for write transactions ('416 Patent, col. 5:38-46).
  • Technical Importance: By decoupling and parallelizing the time-consuming erase step, this method aimed to improve the write performance of flash-based storage systems, making them more competitive with traditional hard disk drives.

Key Claims at a Glance

  • The complaint asserts non-infringement of the patent generally, without specifying claims (Compl. ¶¶ 43-50). Independent claim 1 is representative of the core method.
  • Independent Claim 1 (Method) requires:
    • providing a memory;
    • providing a cache containing a plurality of entries to be written to the memory;
    • detecting in the cache the plurality of entries to be written to memory;
    • erasing a first portion of the memory to accommodate the plurality of entries; and
    • writing to the first portion of the memory, wherein "an erase operation is followed by a plurality of sequential write operations."

U.S. Patent No. 8,093,103 - Multiple Chip Module and Package Stacking Method for Storage Devices

Issued January 10, 2012 ('103 Patent)

The Invention Explained

  • Problem Addressed: The patent notes that traditional semiconductor disk drives use separate packages for components like the controller, memory, and RAM, which limits the potential for miniaturization and density ('103 Patent, col. 1:12-21).
  • The Patented Solution: The invention describes a method for creating high-density storage devices by stacking multiple chip modules (MCMs). It defines a system of "active" and "passive" ports with specific signal routing paths that allow modules to be stacked vertically, enabling a controller on a base module to communicate with a specific module within the stack ('103 Patent, col. 9:1-10; Fig. 19). This modular, stackable design is intended to maximize storage capacity in a small physical footprint ('103 Patent, col. 1:30-41).
  • Technical Importance: This approach to 3D packaging provides a framework for building highly dense and scalable solid-state storage, a key enabler for smaller and more powerful electronic devices.

Key Claims at a Glance

  • The complaint asserts non-infringement generally (Compl. ¶¶ 52-59). Independent claim 1 is representative of the stacking method.
  • Independent Claim 1 (Method) requires, among other elements:
    • providing first and second memory modules with specified connections;
    • forming a "first serial chain route" that includes a serial chain circuit, input, and output;
    • forming a second serial chain route and a "control circuit for enabling a routing path" that connects the first and second serial chain routes within an "end module";
    • the control circuit is disposed to enable the routing path in response to a control signal from another module.

U.S. Patent No. 7,826,243 - Multiple Chip Module and Package Stacking for Storage Devices

Issued November 2, 2010 ('243 Patent)

The Invention Explained

The '243 patent, from which the '103 patent is a divisional, describes a system for creating high-density, scalable storage devices by stacking modular semiconductor components. The invention details specific pin assignment and signal routing techniques, including "active" and "passive" ports and serial chain routes, to enable communication between a base controller and specific layers in a vertical stack of modules ('243 Patent, Abstract; col. 9:1-35).

Key Claims at a Glance

  • Asserted Claims: The complaint does not specify which claims are at issue (Compl. ¶¶ 61-68).
  • Accused Features: The complaint states that Samsung's DRAM and processor/DRAM packages are accused of infringement but alleges they lack the claimed "active port," "passive port," "control circuit," and "routing path" (Compl. ¶¶ 63-67).

U.S. Patent No. 9,135,190 - Multi-Profile Memory Controller for Computing Devices

Issued September 15, 2015 ('190 Patent)

The Invention Explained

This patent describes a memory controller designed to manage a memory store containing different types of memory devices (e.g., with different page or block sizes). The controller uses distinct "device profiles," each containing attributes for a specific memory type, to optimize memory transactions, such as by selecting an optimal transfer size or memory location based on the nature of the data (e.g., random vs. sequential) ('190 Patent, Abstract; col. 1:44-52).

Key Claims at a Glance

  • Asserted Claims: The complaint does not specify which claims are at issue (Compl. ¶¶ 70-77).
  • Accused Features: Samsung's solid state drives are accused, but the complaint alleges they do not use a "device profile optimal for a data type" and do not select a transfer size as a "function of a device profile's attributes" (Compl. ¶¶ 72-76).

III. The Accused Instrumentality

Product Identification

The complaint identifies the accused products as Samsung's "solid state storage drives, stacked electronics components, and products containing the same," including specifically "DRAM and processor/DRAM packages" and "solid state drives" (Compl. ¶¶ 16, 45, 54, 63, 72).

Functionality and Market Context

The complaint describes Samsung as a supplier of "leading consumer electronics, including semiconductor memory chips," such as DRAM and flash memory, which are incorporated into devices like computers and smartphones (Compl. ¶7). The functionality at issue relates to the internal operation of these memory systems, specifically how they manage data storage and retrieval through their controllers and physical interconnects (Compl. ¶¶ 47, 56, 58, 65, 67, 74, 76).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

'416 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
detecting in the cache the plurality of entries to be written to memory The Accused Products do not detect cache entries to be written to memory. ¶47 col. 9:57-58
erasing a first portion of the memory to accommodate the plurality of entries to be written to memory The Accused Products do not erase memory to accommodate the cache entries to be written to memory. ¶47 col. 9:59-61
[Dependent claims require] performing, in parallel, a plurality of erase operations The Accused Products do not perform such parallel operations. ¶49 col. 7:1-6

Identified Points of Contention

  • Technical Question: A central factual dispute will be whether the memory management logic in Samsung's accused SSDs performs functions that meet the claim limitations of "detecting a plurality of entries" and "erasing a portion of memory to accommodate" them. The complaint's denial suggests a fundamental difference in the operational sequence or triggering mechanism for erase and write operations compared to what the patent claims.

'103 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
a first serial chain route that includes at least one serial chain connection... a second serial chain route and a control circuit for enabling a routing path that connects the first serial chain route with the second serial chain route within an end module The Accused Products lack the claimed control circuit and routing path. ¶58 col. 12:7-12
[Implicit in claim 1, explicit in complaint] at least one "active port" and at least one "passive port" The Accused Products lack the claimed active port and passive port. ¶56 col. 11:47-52

Identified Points of Contention

  • Scope Question: The dispute raises the question of whether the physical and logical interconnects within Samsung's DRAM packages can be characterized as having the specific structures claimed, such as an "active port," a "passive port," and a "control circuit" that enables a "routing path" between serial chains. The case may turn on the construction of these terms and whether Samsung's architecture falls within their scope.

V. Key Claim Terms for Construction

For the '416 Patent

  • The Term: "an erase operation is followed by a plurality of sequential write operations"
  • Context and Importance: This phrase in claim 1 is central to the patented method of improving performance. The complaint alleges that the accused products do not perform "parallel" erase operations (Compl. ¶49). Practitioners may focus on whether the claim requires parallel erases or merely that a single erase operation precedes multiple writes, and how this is evidenced in the specification. The relationship between "an erase operation" (singular) and the parallel processing described in the specification raises a potential ambiguity for the court to resolve.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The plain language of claim 1 recites "an erase operation" (singular), which could be argued to not strictly require the parallel execution of multiple erase cycles described in the preferred embodiments.
    • Evidence for a Narrower Interpretation: The specification repeatedly emphasizes that the invention's benefit comes from performing erase cycles "as a group (in 'parallel')" ('416 Patent, col. 5:43-44). The abstract and detailed description focus heavily on this parallel execution, which may be used to argue that the term "an erase operation" should be interpreted in the context of the overall parallel process disclosed.

For the '103 Patent

  • The Term: "active port" and "passive port"
  • Context and Importance: The complaint's non-infringement defense for the '103 and '243 patents hinges on the assertion that the accused products lack these specific structures (Compl. ¶¶ 56, 65). The definition of these terms is therefore critical. Practitioners may focus on whether these terms are limited to the specific ladder-like or rotational stacking architectures shown in the patent figures or if they can be construed more broadly to cover other forms of 3D package interconnects.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent does not appear to provide an explicit textual definition of "active port" or "passive port." A party might argue for a functional definition where any input/output that connects to the main controller is an "active port" and any pass-through connection is a "passive port."
    • Evidence for a Narrower Interpretation: The meaning of these terms is heavily implied by their use in the detailed description and figures, particularly Figure 19 ('103 Patent, col. 9:1-10). A party could argue the terms are defined by these specific embodiments, where an "active port" (e.g., 1904) is a dedicated pad on the controller for a specific module stack and "passive ports" (e.g., 1909) are the repeating, offset connections that form the "ladder-like routing path" (1905) up the stack.

VI. Other Allegations

  • Indirect Infringement: The complaint includes preemptive denials of indirect infringement for all four patents-in-suit. It states that Samsung has not "caused, directed, requested, or facilitated any such infringement, and has not had any specific intent to do so" (Compl. ¶¶ 45, 54, 63, 72).

VII. Analyst’s Conclusion: Key Questions for the Case

This declaratory judgment action, spurred by a parallel ITC proceeding, will likely center on two key areas of dispute for the court to resolve:

  1. Functional Mismatch: For the '416 and '190 patents, a primary issue will be factual and technical: does the operational logic of Samsung's memory controllers and SSDs, as a matter of evidence, perform the specific performance-enhancing functions required by the claims—namely, the parallel scheduling of erase operations ('416) and the use of device profiles to optimize transactions ('190)?

  2. Definitional Scope: For the '103 and '243 patents, the core question is one of claim construction: can the terms "active port," "passive port," and "serial chain route," which are rooted in the specific 3D stacking architectures disclosed in the patents, be construed to cover the interconnect structures within Samsung's accused DRAM and processor/DRAM packages?