BiTMICRO LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: BiTMICRO LLC (Delaware)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff’s Counsel: Bunsow De Mory LLP; George Brothers Kincaid & Horton, L.L.P.
• Case Identification: 6:22-cv-335, W.D. Tex., 03/30/2022
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant Intel maintains places of business in the district and has allegedly committed acts of patent infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor products, including solid-state drives (SSDs), FPGAs, and processors with 3D-stacked architectures, infringe six patents related to memory technology.
• Technical Context: The patents-in-suit address fundamental technologies in semiconductor design and solid-state storage, including chip stacking, multi-profile memory controllers, logical-to-physical address mapping, secure system booting, and power-loss protection.
• Key Procedural History: The complaint alleges that Defendant had actual notice of at least U.S. Patent Nos. 7,826,243 and 9,135,190 since September 5, 2018, as a result of a subpoena Plaintiff served on Defendant in a prior International Trade Commission proceeding (Inv. No. 337-TA-1097). This prior event is cited as a basis for the willfulness allegations for those patents.

Case Timeline

Date	Event
1999-09-21	’939 Patent Priority Date
2002-12-17	’939 Patent Issue Date
2005-12-29	’243 Patent Priority Date
2006-06-08	’740 Patent Priority Date
2009-09-04	’190 Patent Priority Date
2010-11-02	’243 Patent Issue Date
2011-08-30	’740 Patent Issue Date
2013-03-15	’084 & ’694 Patents Priority Date
2015-09-15	’190 Patent Issue Date
2018-01-02	’084 Patent Issue Date
2018-09-05	Alleged notice of ’243 and ’190 Patents to Intel via ITC subpoena
2018-11-06	’694 Patent Issue Date
2022-03-30	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,826,243 - Multiple chip module and package stacking for storage devices

The Invention Explained

• Problem Addressed: The patent addresses the challenge of device miniaturization, noting that prior systems typically arranged processing and memory chips in separate packages, which required a significant amount of physical space (Compl. ¶18; ’243 Patent, col. 1:6-2:2).
• The Patented Solution: The invention proposes stacking multiple semiconductor modules vertically to create a compact, high-capacity package. It describes specific interconnections and signal paths, termed "serial chain routes," that allow signals to travel up and down the stack for communication between modules and for testing purposes (Compl. ¶¶ 17, 20; ’243 Patent, col. 9:61-10:35, Fig. 21a). An "end module" at the top of the stack can contain a control circuit to enable a routing path that connects an upward signal path with a downward signal path (Compl. ¶¶ 20-21).
• Technical Importance: This module and package stacking technique allows for the implementation of large-capacity storage and high-functionality devices in smaller packages, which was critical for the industry trend toward smaller and more powerful electronic devices (Compl. ¶17).

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶72).
• The essential elements of Claim 1 are:
  • A stacked module comprising a plurality of modules, each with one or more active ports and one or more passive ports.
  • A first serial chain route including at least one serial chain connection (comprising a circuit, input, and output).
  • A second serial chain route and a control circuit within an "end module" for enabling a routing path that connects the first and second serial chain routes.
  • The control circuit is disposed to enable this routing path in response to a control signal received from another module in the stack.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 9,135,190 - Multi-profile memory controller for computing devices

The Invention Explained

• Problem Addressed: The patent describes a limitation in prior memory controllers, which were designed to operate with memory locations that all shared the same set of characteristics, such as block size. This restricted the ability to vary how read and write operations were performed on different types of memory (Compl. ¶26; ’190 Patent, col. 1:20-60).
• The Patented Solution: The invention discloses a "multi-profile" memory controller capable of operating differently with various memory locations based on their specific attributes, which are organized into "device profiles" (Compl. ¶27). These profiles can define attributes such as memory type, data size, or memory protocol, allowing the controller to select the optimal memory location and transfer parameters for a given transaction (Compl. ¶27; ’190 Patent, col. 3:14-4:25). An example application is partitioning a non-volatile memory device to create a temporary cache partition that retains data even during a power loss (Compl. ¶25).
• Technical Importance: This approach enables more dynamic and efficient memory management, improving performance and reliability by allowing a single controller to intelligently manage heterogeneous memory resources within a storage device (Compl. ¶¶ 25-26).

Key Claims at a Glance

• The complaint asserts independent claim 59 (Compl. ¶91).
• The essential elements of Claim 59 are:
  • A memory controller with an interface controller and a memory store.
  • The interface controller performs a memory transaction by addressing a first memory location.
  • The first memory location and a second memory location are associated with first and second different "device profiles."
  • The first device profile is optimal for the data type of the transaction (e.g., random or sequential).
  • The interface controller identifies command details, obtains a first set of attributes from the first device profile, and uses those attributes in addressing the first memory location.
  • The addressing includes selecting a transfer size that is a function of the transaction's data size and the first set of attributes.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 8,010,740 - Optimizing memory operations in an electronic storage device

Technology Synopsis

The patent addresses inefficiencies in solid-state storage devices, such as write-cycle limitations and the complexities of block addressing (Compl. ¶31). It proposes a solution using an improved mapping table that associates logical block address (LBA) sets with physical block address (PBA) sets and access parameters, enabling the operational load to be optimally distributed across different storage resources through techniques like interleaving (Compl. ¶¶ 33-34).

Asserted Claims

Independent claim 1 (Compl. ¶126).

Accused Features

Intel's NVMe and Optane SSDs and Optane Persistent Memory (PMem) modules, which allegedly use an "address indirection table" to map logical to physical addresses to optimize memory operations (Compl. ¶¶ 127-128).

U.S. Patent No. 9,858,084 - Copying of power-on reset sequencer descriptor from nonvolatile memory to random access memory & U.S. Patent No. 10,120,694 - Embedded system boot from a storage device

Technology Synopsis

These patents, which share a specification, address inefficient and unreliable boot processes in embedded systems that required loading large amounts of firmware from external storage to RAM (Compl. ¶41). The invention provides for a power-on reset (POR) sequencer that uses a "POR sequencer descriptor" stored in nonvolatile memory to initialize the system. This descriptor can be copied to RAM and its integrity verified before the main system CPUs are activated, providing a more efficient and resilient boot process (Compl. ¶42).

Asserted Claims

’084 Patent, claim 19; ’694 Patent, claim 6 (Compl. ¶¶ 141, 158).

Accused Features

Intel’s Stratix 10 FPGA products, which are alleged to contain a Secure Device Manager (“SDM”) that functions as a POR sequencer, retrieving a configuration bitstream (the descriptor) from nonvolatile flash memory to initialize and boot the system (Compl. ¶¶ 144, 161).

U.S. Patent No. 6,496,939 - Method and system for controlling data in a computer system in the event of a power failure

Technology Synopsis

The patent addresses the problem of data loss from volatile memory during a sudden power failure, noting the disadvantages of prior solutions like batteries and uninterruptible power supplies (UPS) (Compl. ¶48). The invention discloses a system using a plurality of "super capacitors" to provide temporary auxiliary power, enabling newly written or modified data to be flushed from volatile memory to non-volatile memory before the system shuts down (Compl. ¶¶ 47, 49).

Asserted Claims

Independent claim 10 (Compl. ¶172).

Accused Features

Intel’s RAID Controllers with RAID Maintenance Free Backup Units (RMFBU) and its SSDs with Power Loss Protection, which allegedly use energy-storing capacitors to provide backup power to offload cached data from volatile RAM to non-volatile NAND flash in the event of a power failure (Compl. ¶¶ 57-58, 174, 177).

III. The Accused Instrumentality

Product Identification

Intel’s vertically stacked integrated circuits marketed under the Foveros brand, exemplified by the Lakefield Foveros product ('243 Patent); Intel SSDs with SLC caching capabilities (e.g., 660p Series) and Intel Optane Persistent Memory products ('190 Patent) (Compl. ¶¶ 52-54).

Functionality and Market Context

• The Lakefield Foveros product employs a 3D stacking technology where layers of DRAM, a compute chiplet, and a base die are stacked vertically to create a compact, high-performance processor (Compl. ¶73). An Intel presentation diagram included in the complaint shows the product consists of two DRAM layers stacked on a compute module, which is stacked on a base module, and finally a package module (Compl. ¶73, p. 25).
• The Intel 660p Series SSDs are alleged to use a portion of their Quad-Level Cell (QLC) NAND memory to function as a higher-performance Single-Level Cell (SLC) cache (Compl. ¶92). The controller chip manages these two distinct memory regions—the fast but smaller SLC cache and the slower but larger QLC main store—to mitigate the higher latency of QLC NAND and deliver faster data writes (Compl. ¶97). The complaint references a table of specifications for the 660p SSDs, highlighting the SMI 2263 controller chip (Compl. ¶93, p. 37).

IV. Analysis of Infringement Allegations

’7,826,243 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A stacked module comprising a plurality of modules...	The Lakefield Foveros product consists of stacked modules, including DRAM, compute, base, and package layers.	¶73	col. 1:19-21
...each comprising: one or more active ports for carrying one or more active signal;	The Lakefield product has pads on the compute chip that carry active signals, alleged to be "active ports."	¶75	col. 10:44-45
one or more passive ports for passing through the one or more active signals;	The product has passive ball and pad pairs between the compute and SoC chips that allegedly pass active signals through the stack.	¶76	col. 10:46-47
a first serial chain route that includes at least one serial chain connection...	A signal path coupling the ball and pads between the compute module and the SoC module allegedly forms a serial chain connection and route.	¶¶77-78	col. 10:48-52
a second serial chain route and a control circuit for enabling a routing path that connects the first serial chain route with the second...within an end module;	A routing path through the PoP memory module (alleged to be the "end module") connects the first alleged serial route with a second alleged serial route.	¶79	col. 10:53-56
and said control circuit is disposed to enable the routing path in response to a control input signal received from another module...	A control circuit within the compute module allegedly enables the routing path in response to a control signal from the SoC module.	¶80	col. 10:57-60

• Identified Points of Contention:
  • Scope Questions: A central question may be whether the signal paths in the accused Foveros product, as interpreted and annotated by Plaintiff in complaint diagrams (Compl. ¶¶ 77-80, pp. 31-33), meet the specific architectural requirements of a "first serial chain route" and a "second serial chain route" connected within an "end module" as claimed. The defense may argue that the product's general interconnects do not function in the specific manner of the serial chain described in the patent specification.
  • Technical Questions: The complaint alleges the PoP memory module constitutes an "end module" with a control circuit that enables a routing path (Compl. ¶79). A technical question is whether the accused product actually contains a distinct "control circuit" that performs this specific claimed function of enabling a routing path between two separate serial chains in response to a control signal from another module, or if this is an oversimplification of the product's operation.

’9,135,190 Infringement Allegations

Claim Element (from Independent Claim 59)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A memory controller comprising: an interface controller...a memory store; wherein the memory device interface is directly coupled to the memory store;	The 660p SSD includes an SMI 2263 controller chip (interface controller) directly coupled via a memory bus to a QLC NAND memory store.	¶¶93-96	col. 18:36-40
said interface controller disposed to perform a memory transaction by addressing a first memory location in the memory store,	The controller performs write transactions by addressing a location within the SLC cache partition of the memory store.	¶97	col. 18:41-43
said first memory location and a second memory location respectively associated with a first device profile and a second device profile;	A first location in the SLC cache is associated with a first device profile, while a second location in the main QLC store is associated with a second profile.	¶98	col. 18:44-46
wherein said first device profile is optimal for a data type...	The SLC cache profile is alleged to be optimal for random and sequential data writes because it "delivers faster...data writes."	¶99	col. 18:47-50
said interface controller identifies command details...said device profile representing a first set of attributes...and a difference exists between said first and second device profiles;	The controller identifies command details for writing to the SLC cache; the SLC profile (1 bit/cell) and QLC profile (4 bits/cell) are different.	¶¶100-101	col. 18:51-59
said interface controller obtaining the first set of attributes...and said addressing of said first memory location includes using said attributes from said first device profile;	After identifying command details for a write to the SLC cache, the controller chip allegedly obtains the attributes (e.g., data size, protocol) associated with the SLC cache and uses them.	¶102	col. 18:60-62
and said addressing...includes selecting a transfer size for the memory transaction, wherein the transfer size is a function of a data size...and the first set of attributes.	The controller selects a transfer size based on the size of the data to be written and the attributes and available capacity of the SLC cache.	¶103	col. 18:63-65

• Identified Points of Contention:
  • Scope Questions: The dispute may turn on whether the term "device profile" can be construed to cover a controller's dynamic management of different memory cell types (SLC vs. QLC) within a single memory store. The defense could argue this is a firmware-level caching algorithm rather than the use of distinct, formally defined "profiles" as contemplated by the patent.
  • Technical Questions: What evidence does the complaint provide that the accused controller explicitly "obtain[s] the first set of attributes" associated with the SLC cache after identifying command details, as required by the claim sequence? The analysis will raise the question of whether the controller's operation matches this specific claimed process or if the attributes are inherent to the controller's general operating logic.

V. Key Claim Terms for Construction

From the ’243 Patent

• The Term: "serial chain route"
• Context and Importance: This term is the core of the infringement theory against the Foveros products. Its construction will determine whether the signal paths alleged in the accused devices (Compl. ¶¶ 77-79) meet the claim limitation. Practitioners may focus on this term because the complaint's infringement theory relies on interpreting complex, multi-layer interconnects as the specific "routes" claimed.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim itself defines the connection as including "a serial chain circuit, a serial chain input, and serial chain output," language which could be argued to cover a variety of serial connections (’243 Patent, col. 10:50-52).
  • Evidence for a Narrower Interpretation: The specification provides a detailed embodiment in Figure 21a and 21b, showing a specific structure of IN/OUT balls and pads that pass signals up and down the stack (’243 Patent, col. 9:61-10:35). This specific disclosure could be used to argue that the term is limited to structures that operate in a similar way.

From the ’190 Patent

• The Term: "device profile"
• Context and Importance: The infringement case for the SSDs hinges on whether the SLC cache and the main QLC store are each associated with a distinct "device profile." The definition will be critical to determining if a dynamic caching implementation meets this claim element.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification states that attributes are organized into device profiles that can be used "to determine how memory transactions are to be performed" and that attributes can include "type of memory device... data size... memory protocol" (’190 Patent, col. 3:14-18; col. 2:63-3:2). This could support a broad reading covering any set of operational parameters linked to a memory location.
  • Evidence for a Narrower Interpretation: A defendant may argue that the patent's description of organizing attributes into profiles and using them to select an "optimal memory location" implies a more formal, pre-defined data structure than is used in a dynamic caching algorithm, which might be characterized as a firmware process rather than a distinct profile (’190 Patent, col. 3:14-4:25).

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all asserted patents, based on Defendant’s publication of instructional guides, user manuals, and technical documentation that allegedly instruct and encourage customers to use the accused products in an infringing manner (Compl. ¶¶ 85, 120, 134, 151, 165).
• Willful Infringement: Willfulness is alleged for all patents. For the ’243 and ’190 patents, the allegation is based on alleged pre-suit knowledge since September 2018, stemming from an ITC subpoena (Compl. ¶¶ 84, 119). For the remaining patents, the complaint alleges knowledge at least as of the filing of the complaint, suggesting a basis for post-suit willfulness (Compl. ¶¶ 135, 152, 166).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural mapping: can the complex, multi-layer signal paths in the accused Foveros 3D-stacked products, as interpreted by the Plaintiff, be shown to function in the specific manner required by the claimed ‘first and second serial chain routes’ connected within an ‘end module,’ or is there a fundamental mismatch in the routing architecture?
• A second key question will be one of definitional scope: can the term ‘device profile,’ as defined in the patent, be construed to cover a memory controller’s dynamic management of different memory types within a single SSD (such as an SLC cache and a QLC main store), or does the term require a more formally distinct and pre-defined set of attributes than what is implemented in the accused products?
• A significant issue for damages will be knowledge and intent: what evidence beyond participation in a prior ITC proceeding demonstrates Intel's pre-suit knowledge of the asserted patents and a willful disregard of Plaintiff's patent rights, particularly for the four patents not explicitly identified in that earlier proceeding?