DCT
3:25-cv-02170
TurboCode LLC v. Inseego Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: TurboCode LLC (Texas)
- Defendant: Inseego Corp. (Delaware)
- Plaintiff’s Counsel: DNL Zito; Direction IP Law
- Case Identification: 3:25-cv-02170, S.D. Cal., 08/21/2025
- Venue Allegations: Plaintiff alleges venue is proper in the Southern District of California because Defendant has a place of business in the district where it has allegedly committed acts of infringement.
- Core Dispute: Plaintiff alleges that Defendant’s 4G/LTE-capable modems and gateways infringe a patent related to high-speed turbo decoder architectures for error correction in wireless communications.
- Technical Context: The technology concerns turbo codes, a class of high-performance forward error correction codes used to achieve reliable data transfer over noisy communication channels, which are fundamental to modern standards like 4G/LTE.
- Key Procedural History: The patent-in-suit was the subject of an Ex Parte Reexamination, resulting in the issuance of a Reexamination Certificate on February 10, 2009. The asserted claim, Claim 6, was added during this proceeding, which may focus the court’s analysis on the prosecution history of the reexamination.
Case Timeline
| Date | Event |
|---|---|
| 2001-01-02 | U.S. Patent No. 6,813,742 Priority Date |
| 2004-11-02 | U.S. Patent No. 6,813,742 Issues |
| 2006-07-13 | Reexamination Request Filed for ’742 Patent |
| 2009-02-10 | Ex Parte Reexamination Certificate Issues for ’742 Patent |
| 2025-08-21 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,813,742 - "High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture"
The Invention Explained
- Problem Addressed: The patent addresses the challenge of implementing computationally complex Maximum a Posteriori (MAP) decoding algorithms for turbo codes in hardware for wireless devices ('742 Patent, col. 1:49-55). Prior art methods were described as too slow, power-intensive, and costly for consumer products like 3G mobile phones due to their reliance on multiplication-heavy calculations ('742 Patent, col. 1:55-61).
- The Patented Solution: The invention proposes a decoder architecture that uses two pipelined and serially connected Soft-In/Soft-Out (SISO) Log-MAP decoders ('742 Patent, col. 2:40-44). This design replaces complex multiplier circuits with simpler binary adders by operating in the logarithmic domain, which simplifies implementation in ASIC hardware, reduces power consumption, and increases data throughput ('742 Patent, col. 2:53-60; Fig. 4). The pipelined structure allows one decoder to process data from a memory module while the other processes data from a corresponding de-interleaver memory, enabling iterative decoding that produces an output each clock cycle ('742 Patent, col. 2:45-51).
- Technical Importance: This architecture aimed to make high-performance turbo decoding practical and economical for mass-market, power-constrained wireless devices, a key requirement for the rollout of 3G and subsequent mobile communication standards ('742 Patent, col. 2:32-40).
Key Claims at a Glance
- The complaint asserts independent claim 6, which was added via an Ex Parte Reexamination Certificate (Compl. ¶13-14).
- The essential elements of Claim 6 are:
- A method of iteratively decoding received baseband signals.
- Providing an input buffer with at least three shift registers to generate first, second, and third shifted input signals.
- Providing first and second soft decision decoders serially coupled in a circular circuit, where each decoder processes soft decision data from the preceding one.
- The first decoder receives the first and second shifted input signals, and the second decoder receives the third shifted input signal.
- Providing at least one memory module coupled to the output of each decoder.
- The output of the memory module associated with the second decoder is fed back as an input to the first decoder.
- Processing systematic and extrinsic information data using a MAP or logarithm approximation algorithm.
- Generating a soft decision based on the MAP or logarithm approximation algorithm.
- Weighing and storing soft decision information into the corresponding memory module.
- Performing iterative decoding for a predetermined number of times, where an output from the last decoder is fed back to the first, and then propagates through the decoders in a circular circuit.
- The complaint does not explicitly reserve the right to assert dependent claims.
III. The Accused Instrumentality
Product Identification
The Accused Instrumentalities are the "Inseego Skyus SC, Inseego SKYUS 100 Series, other Inseego Skyus series products that include LTE capability, and Inseego SA2100 Gateway" (Compl. ¶13).
Functionality and Market Context
- The complaint alleges these products are wireless communication devices, such as USB modems and gateways, that provide "Enterprise-grade LTE connectivity" (Compl. ¶15). The complaint provides screenshots of product datasheets showing their compliance with 4G/LTE standards (Compl. p. 6-7).
- The core accused functionality is the products' implementation of turbo decoding, which the complaint alleges is required by the 3rd Generation Partnership Project ("3GPP") Standard Specifications for 4G/LTE (Compl. ¶13, ¶15). The complaint includes a diagram from a 3GPP specification illustrating the signal processing chain in a User Equipment (UE) device, which includes a "Decoding + RM" (Rate Matching) block (Compl. p. 7).
IV. Analysis of Infringement Allegations
’742 Patent Infringement Allegations
| Claim Element (from Independent Claim 6) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| providing an input buffer comprising at least three shift registers, for receiving an input signal and generating first, second, and third shifted input signals | The accused products provide an input buffer with at least three shift registers that receives an input signal and generates first, second, and third shifted input signals for the turbo decoder. A diagram depicting an "Input Buffer & External Info. Buffer" feeding "SISO Decoders" is provided as evidence. | ¶16 | col. 4:11-14 |
| providing first and second soft decision decoders serially coupled in a circular circuit, wherein each decoder processes soft decision from the preceding decoder output data... | The accused products provide first and second soft decision decoders connected in series in a looped manner, where each processes soft information from the other to refine accuracy through iterative feedback. | ¶17 | col. 4:8-14 |
| providing at least one memory module coupled to an output of each of the first and second soft decision decoders, wherein the output of the memory module associated with the second soft decision decoder is fed back as an input of the first soft decision decoder | The accused products include memory modules (identified as "interleaver" and "deinterleaver") coupled to the decoders, where the output of the memory associated with the second decoder (SISO 2) is fed back as an input to the first decoder (SISO 1). This is supported by a diagram showing a parallel turbo decoding architecture. | ¶18 | col. 10:1-9 |
| processing systematic information data and extrinsic information data using the maximum a posteriori (MAP) probability algorithm, and/or logarithm approximation algorithm | The accused products process systematic and extrinsic data using at least the BCJR algorithm, a form of the MAP algorithm, for turbo decoding. | ¶19 | col. 10:20-25 |
| generating soft decision based on the maximum a posteriori (MAP) probability algorithm, and/or logarithm approximation algorithm | The accused products generate soft decisions using the BCJR algorithm. | ¶20 | col. 10:35-40 |
| weighing and storing soft decision information into the corresponding memory module | The accused products weigh (or "normalize") and store soft decision information in a corresponding memory module (e.g., an interleaver). The complaint points to a diagram where the output of a "SISO 1" decoder is stored in an associated "interleaver memory module II." | ¶21 | col. 10:40-42 |
| performing, for a predetermined number of times, iterative decoding... wherein an output from the last soft decision decoder is fed back as an input to the first soft decision decoder...and propagate to the last decoder in a circular circuit | The accused products perform a predetermined number of iterations, where the output of the second decoder ("SISO 2") is fed back as an input to the first decoder ("SISO 1") to complete a circular circuit. | ¶22 | col. 10:43-50 |
Identified Points of Contention
- Scope Questions: The complaint relies heavily on general technical diagrams of turbo decoders and references to the LTE standard. A central question will be whether Inseego's specific implementation of the LTE-required turbo decoder in its products meets every limitation of Claim 6. The defense may argue that non-infringing alternatives exist to comply with the standard or that its architecture differs materially from the claim's requirements.
- Technical Questions: What evidence does the complaint provide that the accused products perform the specific "weighing and storing" step as claimed? The complaint asserts that any MAP algorithm "necessarily requires weighing (or 'normalization')" (Compl. ¶21), a conclusory statement that may require expert testimony to substantiate in the context of the accused products' actual operation.
V. Key Claim Terms for Construction
- The Term: "soft decision decoders serially coupled in a circular circuit"
- Context and Importance: This term defines the core architecture of the claimed method. The infringement analysis depends on whether the accused LTE decoders, which are often depicted as parallel concatenated decoders, fall within the scope of this "serially coupled in a circular circuit" language. Practitioners may focus on this term because the patent's own description emphasizes a specific pipelined, serial data flow between two distinct decoders (Decoder A and Decoder B) to achieve high throughput ('742 Patent, col. 2:40-51; Fig. 4).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim uses the general term "circular circuit," which could be argued to cover any iterative decoding scheme where information is passed between decoders, including the parallel structures common in LTE. Claim 6 also describes a feedback loop from the "last soft decision decoder" to the "first," which is characteristic of iterative decoding generally.
- Evidence for a Narrower Interpretation: The specification repeatedly describes a specific "pipelined scheme" with two decoders, A and B, operating sequentially on data blocks ('742 Patent, col. 2:45-51, Abstract). The detailed description of Figure 4 shows a distinct serial arrangement where the output of Decoder A feeds Decoder B through an interleaver memory, and the output of B feeds back to A through a de-interleaver memory ('742 Patent, col. 4:8-26). This may support a narrower construction tied to this pipelined architecture.
VI. Other Allegations
The complaint does not provide sufficient detail for analysis of indirect or willful infringement. It contains a single count for direct infringement (Compl. ¶13) and a general allegation of "constructive notice" (Compl. ¶24), but no specific factual allegations to support claims for induced infringement, contributory infringement, or willfulness.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of technical implementation vs. standard compliance: Will TurboCode be able to prove that compliance with the 4G/LTE standard, as alleged, necessarily requires practicing the specific multi-step method of Claim 6, or will Inseego demonstrate that its products use a standard-compliant but non-infringing decoder architecture?
- A second key issue will be one of claim scope and architecture: Can the phrase "serially coupled in a circular circuit," which is rooted in the patent's disclosure of a specific pipelined architecture, be construed broadly enough to read on the parallel concatenated convolutional code (PCCC) decoder architectures commonly associated with the LTE standard and depicted in the complaint's supporting evidence? The outcome of this claim construction dispute may be dispositive.