DCT

1:19-cv-00426

VLSI Technology LLC v. Intel Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:19-cv-00426, D. Del., 03/01/2019
  • Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant Intel is incorporated in Delaware.
  • Core Dispute: Plaintiff alleges that Defendant’s microprocessors, including the Cannon Lake, Broadwell, and Skylake product families, infringe six patents related to power consumption management, on-chip voltage regulation, memory architecture, and data processing protocols.
  • Technical Context: The technologies at issue concern fundamental aspects of modern high-performance microprocessor design, particularly methods for dynamically managing power and performance to improve efficiency.
  • Key Procedural History: The complaint alleges that Intel maintained a corporate policy of forbidding its engineers from reading patents held by outside companies, which Plaintiff frames as evidence of willful blindness. The complaint also references a prior lawsuit filed by VLSI against Intel in the same district involving a patent with a common inventor, which may be used to support allegations of knowledge.

Case Timeline

Date Event
2000-11-20 U.S. Patent No. 6,366,522 Priority Date
2000-11-20 U.S. Patent No. 6,633,187 Priority Date
2002-04-02 U.S. Patent No. 6,366,522 Issued
2003-10-14 U.S. Patent No. 6,633,187 Issued
2004-06-21 U.S. Patent No. 7,606,983 Priority Date
2005-06-29 U.S. Patent No. 7,725,759 Priority Date
2006-07-31 U.S. Patent No. 7,292,485 Priority Date
2007-11-06 U.S. Patent No. 7,292,485 Issued
2008-03-28 U.S. Patent No. 7,793,025 Priority Date
2009-10-20 U.S. Patent No. 7,606,983 Issued
2010-05-25 U.S. Patent No. 7,725,759 Issued
2010-09-07 U.S. Patent No. 7,793,025 Issued
2016-03-31 Accused Broadwell Server Processors Launch Date (Q1'16)
2018-06-30 Accused Cannon Lake Processors Launch Date (Q2'18)
2019-03-01 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,366,522 - "Method and apparatus for controlling power consumption of an integrated circuit"

  • Issued: April 2, 2002

The Invention Explained

  • Problem Addressed: The patent describes that integrated circuits are typically designed with a supply voltage and system clock set to handle the most demanding applications, which results in excessive power consumption when performing less taxing tasks (’522 Patent, col. 1:36-44). This creates a need for a method to adjust the system clock and/or supply voltage based on the specific application being performed and the circuit's capabilities, in order to conserve power (’522 Patent, col. 1:45-48).
  • The Patented Solution: The invention provides a method and apparatus where a computational engine produces control signals for both the system clock and an on-chip power supply (’522 Patent, col. 2:19-27). These signals are based on the "processing transfer characteristic" of the engine and the "processing requirements" of the application currently running, allowing power consumption to scale dynamically with the workload (’522 Patent, Abstract).
  • Technical Importance: This approach, known generally as dynamic voltage and frequency scaling (DVFS), became a foundational technology for managing the trade-off between performance and power consumption in mobile devices and data centers.

Key Claims at a Glance

  • The complaint asserts independent claim 9 (Compl. ¶15).
  • The essential elements of claim 9 are:
    • producing a system clock from a reference clock based on a system clock control signal;
    • regulating at least one supply from a power source and an inductance based on a power supply control signal; and
    • producing the system clock control signal and the power supply control signal based on a processing transfer characteristic of a computation engine and processing requirements associated with processing at least a portion of an application by the computation engine.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 6,633,187 - "Method and apparatus for enabling a stand alone integrated circuit"

  • Issued: October 14, 2003

The Invention Explained

  • Problem Addressed: The patent identifies a difficulty in starting up a "stand-alone integrated circuit" that includes an on-chip power converter, because the power converter itself may require a clock signal to generate the very supply voltage needed by the digital circuitry that produces the clock (’187 Patent, col. 1:34-39).
  • The Patented Solution: The invention proposes a sequential start-up method. First, the circuit is held in an idle or reset state when power is applied. Upon receiving a "power enable signal," an on-chip power converter is enabled to generate a supply. Only after this supply has reached a "steady-state condition" is the full functionality of the integrated circuit enabled, resolving the circular dependency (’187 Patent, Abstract; col. 1:40-42).
  • Technical Importance: This technology provides a robust power-on sequence for complex systems-on-chip (SoCs) that integrate their own voltage regulators, a design that became common for improving power efficiency and reducing component count.

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶48).
  • The essential elements of claim 1 are:
    • establishing an idle state that holds at least a portion of the stand-alone IC in a reset condition when a power source is coupled to it;
    • receiving a power enable signal;
    • enabling, in response to the signal, an on-chip power converter to generate at least one supply from the power source, wherein the enabling includes generating a clock signal, generating power converter regulation signals based on the clock, and enabling a band-gap reference used in generating the regulation signals; and
    • when the supply has substantially reached a steady-state condition, enabling functionality of the stand-alone IC.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 7,292,485 - "SRAM having variable power supply and method therefor"

  • Issued: November 6, 2007
  • Technology Synopsis: The patent addresses the trade-off in Static Random-Access Memory (SRAM) design between cell stability (for reliable data retention) and write performance (the ability to change a cell's state) (’485 Patent, col. 1:36-38). The invention describes a method to improve write margins by selectively reducing the power supply voltage to a line of memory cells chosen for a write operation, making them easier to overwrite, while maintaining a higher voltage for other cells to ensure stability (’485 Patent, Abstract).
  • Asserted Claims: At least Claim 12 is asserted (Compl. ¶81).
  • Accused Features: The complaint alleges that Intel’s Broadwell processors, which utilize "write-assist technology" in their SRAM arrays, infringe the ’485 Patent (Compl. ¶¶80, 83).

U.S. Patent No. 7,606,983 - "Sequential ordering of transactions in digital systems with multiple requestors"

  • Issued: October 20, 2009
  • Technology Synopsis: The patent addresses the problem of managing access to shared resources like memory in digital systems with multiple processors or functional modules (’983 Patent, col. 1:19-22). It proposes an "improved transaction ordering policy" where individual access requests can specify whether they must be performed in a particular order relative to other requests, providing flexibility beyond strict first-in-first-out (FIFO) or fully unordered systems (’983 Patent, col. 4:57-60).
  • Asserted Claims: At least Claim 11 is asserted (Compl. ¶121).
  • Accused Features: The complaint alleges that Intel products implementing the Intel Quick Path Interconnect ("QPI") Link Layer, such as Broadwell Server processors, infringe the ’983 Patent (Compl. ¶120).

U.S. Patent No. 7,725,759 - "System and method of managing clock speed in an electronic device"

  • Issued: May 25, 2010
  • Technology Synopsis: The patent describes a method for managing clock frequency by monitoring multiple "master devices" (e.g., processor cores) coupled to a bus (’759 Patent, col. 1:46-48). When a master device experiences a "predefined change in performance" (e.g., due to increased workload), it can send a request to a controller to increase a high-speed clock frequency for itself and other devices on the bus, allowing for responsive performance scaling (’759 Patent, Abstract).
  • Asserted Claims: At least Claim 1 is asserted (Compl. ¶152).
  • Accused Features: The complaint alleges that Intel products using Hardware-Controlled Performance States ("HWP" or "Speed Shift") technology, such as Skylake processors, infringe the ’759 Patent (Compl. ¶151).

U.S. Patent No. 7,793,025 - "Hardware managed context sensitive interrupt priority level control"

  • Issued: September 7, 2010
  • Technology Synopsis: The patent describes an interrupt controller that can switch interrupt priority levels with reduced latency based on the system's "context" (’025 Patent, Abstract). It uses a mode control selector to choose between different sets of pre-defined priority level assignments, allowing for rapid changes in interrupt handling based on system state, such as power management or security modes (’025 Patent, col. 1:10-12, Abstract).
  • Asserted Claims: At least Claim 1 is asserted (Compl. ¶180).
  • Accused Features: The complaint alleges that Intel products using "infringing interrupt routing technology," such as Ivy Bridge processors with their "Power Aware Interrupt Routing" system, infringe the ’025 Patent (Compl. ¶¶179, 182).

III. The Accused Instrumentality

Product Identification

  • The complaint accuses a range of Intel processors, with specific infringement examples focused on the "Cannon Lake," "Broadwell," "Broadwell Server," "Skylake," and "Ivy Bridge" generations (Compl. ¶¶16, 49, 82, 122, 153, 181).

Functionality and Market Context

  • The accused products are high-performance microprocessors that form the core of many computing devices. The complaint focuses on specific technical features alleged to be infringing, including:
    • Speed Shift / Hardware-Controlled Performance States (HWP): Technology that allows the processor to autonomously and rapidly select operating frequency and voltage to optimize performance and power efficiency (Compl. ¶¶14, 31, 151).
    • Fully Integrated Voltage Regulator (FIVR): An on-chip power converter that regulates output supply voltage for different domains within the processor, controlled by a Power Control Unit (PCU) (Compl. ¶¶14, 23-24). The complaint presents a diagram showing the FIVR architecture with its on-die controller and package-level inductors (Compl. p. 7).
    • SRAM with write-assist technology: On-chip memory arrays that employ specialized circuits to improve write performance (Compl. ¶80).
    • Quick Path Interconnect (QPI): A high-speed point-to-point processor interconnect technology used for communication between processors and I/O hubs in server platforms (Compl. ¶120).
    • Power Aware Interrupt Routing (PAIR): A system for routing interrupts to processor cores based on their power state to improve efficiency (Compl. ¶¶182-183).

IV. Analysis of Infringement Allegations

U.S. Patent No. 6,366,522 Infringement Allegations

Claim Element (from Independent Claim 9) Alleged Infringing Functionality Complaint Citation Patent Citation
a method for controlling power consumption of an integrated circuit, the method comprises the steps of: Intel Cannon Lake processors are operated using such a method (Compl. ¶16). ¶16 col. 2:7-9
producing a system clock from a reference clock based on a system clock control signal; The Intel power control architecture allegedly produces scalable system clocks from a reference clock using system clock control signals (Compl. ¶19). The complaint includes a diagram of the "IVB Clock Domains" to illustrate this process (Compl. p. 5). ¶18-19 col. 2:10-13
regulating at least one supply from a power source and an inductance based on a power supply control signal; and The Fully Integrated Voltage Regulator (FIVR) allegedly regulates an output supply from a power source and an inductance (Pkg L) based on power supply control signals from the Power Control Unit (PCU) (Compl. ¶23). ¶22-24 col. 2:14-18
producing the system clock control signal and the power supply control signal based on a processing transfer characteristic of a computation engine and processing requirements associated with processing at least a portion of an application by the computation engine. The PCU allegedly produces control signals based on a "quadratic model of the VF requirements" (the processing transfer characteristic) and on the "applied workload" (the processing requirements) to set processor P-states via the HWP system (Compl. ¶¶27, 31). The complaint provides a voltage-frequency curve illustrating power scaling (Compl. p. 8). ¶26-31 col. 2:19-27
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the term "processing transfer characteristic," which the patent describes in the context of a "training module" that experimentally determines performance (’522 Patent, col. 3:45-56), can be construed to read on the "quadratic model of the VF requirements" allegedly used by Intel’s PCU (Compl. ¶27).
    • Technical Questions: What is the evidentiary basis for the allegation that Intel's HWP system, which "autonomously selects performance states as deemed appropriate for the applied workload" (Compl. ¶31), produces control signals based on both a "transfer characteristic" and "processing requirements associated with...an application" in the specific manner required by the claim?

U.S. Patent No. 6,633,187 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a) establishing an idle state that holds at least a portion of the stand-alone IC in a reset condition when a power source is operably coupled to the stand-alone IC; Intel Broadwell processors allegedly initialize into an idle state that holds the cores in a reset condition until correct power sequencing signals are received (Compl. ¶52). ¶51-52 col. 1:46-49
b) receiving a power enable signal; The processors allegedly receive a power enable signal, such as PROCPWRGD, as shown in a "Power Sequencing Signals" table from a datasheet (Compl. pp. 16-17). ¶53-54 col. 2:4-5
c) enabling, in response to the power enable signal, an on-chip power converter of the stand-alone IC to generate at least one supply from the power source, wherein the enabling includes: In response to signals like PROCPWRGD, the PCU allegedly turns on power "rails" provided by an on-chip FIVR, which then provides supply voltages (Compl. ¶56). ¶55-57 col. 2:5-7
generating a clock signal; and generating power converter regulation signals based on the clock signal; The Frequency Control Module in the FIVR allegedly generates a clock signal (e.g., via a "triangular waveform synthesizer") and uses it to generate power converter regulation signals (Compl. ¶60). ¶59-60 col. 4:1-2
enabling a band-gap reference that is used in generating the power converter regulation signals; and The processors allegedly use a band-gap reference (BGREF) to generate power converter regulation signals by measuring "digital VCC power-up" (Compl. ¶62). ¶61-62 col. 4:3-6
d) when the at least one supply has substantially reached a steady-state condition, enabling functionality of the stand-alone IC. The processors allegedly use a "power-on detector" (POD) to enable functionality once supply voltages have reached their steady-state operating level (Compl. ¶66). ¶65-66 col. 2:9-12
  • Identified Points of Contention:
    • Scope Questions: Does Intel's use of a "power-on detector" (Compl. ¶66) to determine that supply voltages are stable constitute "enabling functionality" in the manner claimed, or is there a functional distinction? The definition of "steady-state condition" will be critical.
    • Technical Questions: The complaint links several discrete technical features from different public documents (e.g., a datasheet's power sequencing signals, a technical paper on FIVR architecture, another paper on a band-gap detector). A potential question is whether these separate components operate together in the accused products to perform the full, sequential method as recited in Claim 1.

V. Key Claim Terms for Construction

For the ’522 Patent:

  • The Term: "processing transfer characteristic of a computation engine"
  • Context and Importance: This term is at the heart of how the patented system determines the appropriate clock and voltage levels. Its construction will be critical for determining whether Intel's alleged use of a "quadratic model of the VF requirements" (Compl. ¶27) falls within the scope of the claims.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification provides examples of such characteristics, including "propagation delays through logic circuits, slew rates of transistors..., read/write processing speed, et cetera" (’522 Patent, col. 3:51-55). This language may support a broad definition covering any inherent performance-related electrical property of the circuitry.
    • Evidence for a Narrower Interpretation: The detailed description emphasizes a "training module" that experimentally determines the correct supply voltage for a given function by running it and observing the result (’522 Patent, col. 3:45-col. 4:18, FIG. 4). This could support a narrower interpretation requiring an empirical characterization or learning process, rather than a pre-determined mathematical model.

For the ’187 Patent:

  • The Term: "steady-state condition"
  • Context and Importance: The final step of the claimed start-up sequence—enabling the IC's functionality—is conditioned on the power supply reaching this state. The definition of this term is therefore dispositive for infringement of this limitation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The term is a standard one in electrical engineering, and a party could argue it should be given its plain and ordinary meaning of a stable, non-transient operating level.
    • Evidence for a Narrower Interpretation: The specification provides a specific, quantitative example, stating that a supply lock circuit determines a steady state is reached "when the supply reaches at least 90% of its desired value" (’187 Patent, col. 3:1-3). A party may argue this disclosure limits the term to this or a similar threshold-based definition.

VI. Other Allegations

  • Indirect Infringement: For each asserted patent, the complaint alleges both induced and contributory infringement. Inducement is based on allegations that Intel provides documentation, datasheets, and developer's manuals that instruct customers on using the accused products in an infringing manner (e.g., Compl. ¶¶34, 68). Contributory infringement is based on allegations that the accused processors are material parts of the claimed inventions and are not staple articles of commerce suitable for substantial noninfringing use (e.g., Compl. ¶¶35, 69).
  • Willful Infringement: The complaint alleges willful infringement for all asserted patents. The allegations are based on both post-suit knowledge (from the service of the complaint itself) and alleged pre-suit willful blindness (Compl. ¶¶39, 73). The willful blindness theory is predicated on Intel's alleged corporate policy of forbidding its employees from reading third-party patents, which Plaintiff claims was intended to avoid liability for infringement (Compl. ¶¶33, 67).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can technical terms from the patents, rooted in the context of early 2000s semiconductor technology (e.g., "processing transfer characteristic," "power enable signal"), be construed to cover the sophisticated, model-based, and autonomous power management systems (e.g., HWP, FIVR) implemented in Intel's modern processors?
  • A key evidentiary question will be one of technical integration: does the complaint's evidence, which pieces together information from datasheets, reverse engineering, and technical papers, sufficiently demonstrate that the disparate accused features operate together in a single, integrated process that practices every step of the asserted method claims in the required sequence?
  • A central legal question will be one of willful blindness: can Plaintiff establish that Intel’s alleged corporate policy of not reviewing third-party patents rises to the level of deliberate or reckless disregard of a known risk of infringement required to support a finding of pre-suit willfulness?