DCT

1:21-cv-00525

Rex Computing Inc v. Cerebras Systems Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:21-cv-00525, D. Del., 05/04/2021
  • Venue Allegations: Plaintiff alleges venue is proper as Defendant is a Delaware corporation that conducts business in and resides in the judicial district.
  • Core Dispute: Plaintiff alleges that Defendant’s deep learning computer systems infringe three patents related to network-on-chip architecture, optimized workload assignment for multi-core processors, and efficient instruction implementation.
  • Technical Context: The technology concerns high-performance, massively parallel processor architectures designed to increase efficiency and performance for large-scale computing tasks, particularly in the field of artificial intelligence.
  • Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of Plaintiff’s technology and patent applications through a 2017 Stanford University presentation, as well as through a shared advisor and investors. A significant portion of the complaint is dedicated to alleging that Defendant, in multiple 2020 presentations, copied a technical diagram of Plaintiff's "Neo Chip" architecture first published by Plaintiff in 2015. Plaintiff sent a formal notice letter regarding infringement in April 2021. Subsequent to the complaint filing, an inter partes review (IPR) was instituted against U.S. Patent No. 10,355,975. The proceeding concluded with a certificate issued on January 26, 2024, confirming the patentability of all challenged claims (1-19).

Case Timeline

Date Event
2013-01-01 Plaintiff began developing its Neo Architecture
2015-03-11 Plaintiff's website first portrayed its Neo Chip diagram
2016-01-01 Defendant Cerebras founded
2016-10-19 Priority Date for ’975, ’968, and ’043 Patents
2017-02-01 Plaintiff gave presentation at Stanford allegedly viewed by Defendant's personnel
2018-11-13 U.S. Patent No. 10,127,043 Issued
2019-07-16 U.S. Patent No. 10,355,975 Issued
2020-06-30 U.S. Patent No. 10,700,968 Issued
2021-04-12 Plaintiff sent notice letter to Defendant
2021-05-04 Complaint Filing Date
2022-03-22 IPR filed against the ’975 Patent
2024-01-26 IPR Certificate issued confirming patentability of claims 1-19 of the ’975 Patent

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,355,975 - “Latency Guaranteed Network on Chip” (Issued Jul. 16, 2019)

The Invention Explained

  • Problem Addressed: The patent describes conventional multi-core processor architectures as suffering from complexity, increased latency, and high power consumption due to their reliance on cache hierarchies, cache coherency policies, and virtual memory address translation (’975 Patent, col. 3:41-4:22).
  • The Patented Solution: The invention proposes a cache-less, network-on-chip architecture composed of numerous "tiles," where each tile contains a processor core and an associated router arranged in a grid (’975 Patent, Fig. 2; col. 4:36-54). To manage data flow and avoid the unpredictability of cache-based systems, the routers use a deterministic "static priority routing policy" to handle traffic conflicts based on unchanging priority levels assigned to their input ports, thereby enabling guaranteed latency (’975 Patent, col. 12:5-14). The system also includes an "optimization module" that assigns computational functions to specific groups of tiles, choosing between square or linear tile configurations based on which shape allows the function to execute optimally (’975 Patent, col. 17:46-18:4).
  • Technical Importance: This architectural approach aims to deliver predictable performance and higher power efficiency for massively parallel computing applications by eliminating the overhead associated with traditional cache and virtual memory management systems (’975 Patent, Abstract).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶53).
  • The essential elements of Claim 1 include:
    • A system with a set of processor cores and a corresponding set of routers, where each core-router pair forms a "tile."
    • The tiles are communicatively coupled to form a network where routers can send data packets based on a physical destination address.
    • Each router can retain a data packet during a "traffic condition" and implements a "static priority routing policy."
    • An "optimization module" is configured to determine optimal function assignments and assign frequently communicating functions to adjacent tile groups.
    • The assignment uses "square configurations when the function executes optimally" in a square shape and "linear configurations when the function executes optimally" in a linear shape.

U.S. Patent No. 10,700,968 - “Optimized Function Assignment in a Multi-Core Processor” (Issued Jun. 30, 2020)

The Invention Explained

  • Problem Addressed: In a large-scale, multi-core processor network, the physical location of a task can significantly impact communication performance, and there is a need to ensure that high-priority tasks are not delayed by network congestion caused by less critical tasks (’968 Patent, col. 16:17-24).
  • The Patented Solution: The patent discloses a method for optimizing function placement on a network-on-chip grid that uses a static priority routing policy. The method involves receiving an application, identifying a "high priority function" within that application, and then identifying the hardware "tiles with high routing priority" based on the fixed routing rules of the network (’968 Patent, Fig. 7B). The system then assigns the high-priority software function to execute on the high-priority hardware tiles, thereby aligning software priority with hardware-level network priority (’968 Patent, col. 20:30-44).
  • Technical Importance: This invention provides a method to systematically leverage the deterministic nature of a static routing network to ensure that logically critical computational functions receive preferential data transmission, enhancing overall application performance (’968 Patent, col. 16:53-65).

Key Claims at a Glance

  • The complaint asserts independent claim 19 (Compl. ¶79).
  • The essential steps of method Claim 19 include:
    • Receiving a user application with functions for execution on a multi-core chip composed of tiles.
    • Each router on the chip implements the same "deterministic static priority routing policy," which involves assigning "unchanging priority levels to the input ports."
    • Receiving an identification of a "high priority function."
    • Identifying one or more "tiles with high routing priority" according to the static routing policy.
    • Assigning execution of the high priority function to those identified tiles.
    • Executing the function according to the assignment.

U.S. Patent No. 10,127,043 - “Implementing Conflict-Free Instructions for Concurrent Operation on a Processor” (Issued November 13, 2018)

Technology Synopsis

This patent discloses a system for implementing Very Long Instruction Words (VLIW), which bundle multiple operations into a single instruction for parallel execution within a processor. The invention allows for flexible instruction encoding by enabling "allocable bits" from one instruction's data field to be dynamically used by an adjacent instruction within the same VLIW, based on the specific operations being performed (’043 Patent, Abstract). (Compl. ¶18).

Asserted Claims

The complaint asserts independent claim 1 (Compl. ¶96).

Accused Features

The complaint alleges on information and belief that the processing elements in the Accused Products use instructions with opcodes and value fields that include "allocable bits," citing a Cerebras patent application as evidence of the accused instruction format (Compl. ¶¶98-101).

III. The Accused Instrumentality

Product Identification

The Cerebras CS-1 and CS-2 deep learning computer systems, which incorporate the Cerebras Wafer Scale Engine (WSE/WSE-2), the Cerebras Swarm communication fabric, and the Cerebras Graph Compiler (Compl. ¶¶5, 21).

Functionality and Market Context

The Accused Products are described as large-scale computer systems designed for artificial intelligence and deep learning workloads (Compl. ¶5). The Wafer Scale Engine is a single chip containing a massive number of processor cores (Compl. ¶23). The Swarm communication fabric is characterized as a "massive on-chip communication fabric" that software configures to create a "unique and optimized communication path" for each neural network (Compl. ¶24). The Cerebras Graph Compiler is a software tool that takes a user's neural network model and "generates a placement and routing" of the model's computational kernels onto the WSE's cores to "minimize communication latency" (Compl. ¶25). A diagram in the complaint depicts the Cerebras Wafer Scale Engine as a grid-like arrangement of processing tiles (Compl. ¶56).

IV. Analysis of Infringement Allegations

’975 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a set of processor cores; a set of routers... wherein each processor core and corresponding router form a tile... The Cerebras CS-1 includes a set of processor cores and routers, where each core and its corresponding router form a "tile" on the Wafer Scale Engine. ¶55, ¶57 col. 4:49-62
each router is communicatively coupled with one or more adjacent routers... Each router connects to the routers of its four neighboring tiles, allowing data to be sent to left, right, top, and bottom neighbors. ¶58 col. 5:1-12
each router is operable to retain a data packet in the event of a traffic condition... The accused router has "hardware queues" and buffering capabilities to manage traffic flow and avoid deadlock. ¶60 col. 11:7-10
each router implements a static priority routing policy; Communication between processors occurs along "predetermined routes," and the system uses "statically configured" virtual channels. ¶61 col. 12:5-14
an optimization module configured to: determine optimal function assignment configurations for groups of tiles... The Cerebras Graph Compiler serves as the optimization module, determining how to map neural network "kernels" onto the processor cores by "Choosing the Optimal Mapping Strategy." ¶62-63 col. 17:56-61
...assign... functions... to groups of tiles communicatively coupled in square configurations when the function executes optimally... and... linear configurations when the function executes optimally... The Graph Compiler is configured to implement kernels as a "square or rectangular array of processors" and can "make all kinds of different shapes" to optimize execution. ¶66 col. 17:62-18:4
  • Identified Points of Contention:
    • Scope Questions: A potential issue is whether the accused "Cerebras Graph Compiler," which maps "neural network kernels" and "layers," falls within the scope of the claimed "optimization module," which assigns "functions." The court may need to determine if these terms are synonymous in the context of the patent.
    • Technical Questions: Claim 1 requires that the assignment to square or linear configurations be based on where the function "executes optimally." The complaint alleges the accused compiler creates different shapes, but the primary drivers for placement are described as maximizing locality and minimizing routing distance (Compl. ¶25, fn. 7; ¶63, fn. 34). This raises the question of whether the accused system performs the specific optimality analysis required by the claim language.

’968 Patent Infringement Allegations

Claim Element (from Independent Claim 19) Alleged Infringing Functionality Complaint Citation Patent Citation
receiving a user application, wherein the user application includes a set of functions to be executed by a multi-core microprocessor chip... The Cerebras Graph Compiler is configured to take a "user-specified neural network" as input for execution on the multi-core CS-1 system. ¶81 col. 19:35-37
...each router... implements the same deterministic static priority routing policy, wherein the... policy comprises assigning unchanging priority levels to the input ports... The accused system's routers are alleged to implement a "statically configured" routing policy using "predetermined routes," which corresponds to the claimed policy. ¶83 col. 13:1-10
receiving an identification of a high priority function of the set of functions; The compiler is alleged to identify important functions, for example by determining that "compute-heavy layers get larger PEs allocations." ¶84, ¶64 col. 16:17-24
identifying one or more tiles with high routing priority according to the static priority routing policy; The complaint alleges the compiler identifies optimal physical regions on the wafer to place functions in order to "maximize their communication." ¶84, ¶31 fn. 49 col. 16:34-52
assigning execution of the high priority function to the one or more tiles with high routing priority... The compiler "maps every kernel onto a physical region of the computational array of cores" and "places layers on the fabric to optimize compute and communication." A diagram illustrates this placement strategy (Compl. ¶64). ¶84, ¶81 fn. 46 col. 20:41-44
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the compiler's analysis of a neural network to identify "compute-heavy layers" constitutes "receiving an identification of a high priority function" as required by the claim. A defendant could argue this language requires an explicit priority designation rather than an inferred computational characteristic.
    • Technical Questions: The complaint alleges the accused compiler places functions to "maximize locality" and "minimize routing distances" (Compl. ¶25, fn. 7). This raises an evidentiary question: does this optimization strategy equate to the specific claimed step of identifying and assigning functions to tiles because of their "high routing priority" under the network's static policy?

V. Key Claim Terms for Construction

Terms from the ’975 Patent

  • The Term: "optimization module"
  • Context and Importance: This term's construction is critical, as it is mapped to the Cerebras Graph Compiler. A narrow construction could place the accused software outside the claim's scope. Practitioners may focus on whether the specific decision logic recited in the claim—choosing between square and linear shapes based on optimal execution—is a mandatory feature of the "module" or merely an example of its function.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the module's purpose broadly as functionality "to assign processes (or functions) of an application... so as to optimize execution" (’975 Patent, col. 16:50-54).
    • Evidence for a Narrower Interpretation: Claim 1 itself defines the module by its specific capability to assign functions to "square configurations when the function executes optimally when executed by" a square group and likewise for "linear configurations." This suggests the module must perform this specific comparative analysis.

Terms from the ’968 Patent

  • The Term: "receiving an identification of a high priority function"
  • Context and Importance: This term defines the trigger for the claimed optimization method. The infringement theory depends on equating the compiler's analysis of a neural network with "receiving" this identification.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes a high priority function as one that is "essential to the execution of the application" or for which "responsive/fast execution... is required/preferred" (’968 Patent, col. 16:20-23), suggesting a functional definition rather than a formal one.
    • Evidence for a Narrower Interpretation: The claim's use of the verb "receiving" could be construed to require that the identification is provided to the system as an input, rather than being a property that the system determines or infers through its own analysis of factors like computational load.

VI. Other Allegations

  • Indirect Infringement: For all three patents, the complaint alleges induced infringement based on Defendant’s marketing, sales, customer presentations, and instructions on how to use the Accused Products (Compl. ¶¶69, 86, 103). It alleges contributory infringement on the grounds that the Accused Products are a material component of the patented systems, are sold knowing of their use in an infringing manner, and are not staple articles of commerce (Compl. ¶¶71, 88, 105).
  • Willful Infringement: The complaint alleges willful infringement based on Defendant's alleged pre-suit knowledge of the patents and technology. This alleged knowledge stems from a 2017 Stanford presentation by Plaintiff, interactions with a shared advisor and investors, Defendant's alleged copying of Plaintiff's technical diagrams in 2020, and a formal notice letter sent by Plaintiff in April 2021 (Compl. ¶¶44-48, 72, 89, 106).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can terms rooted in the patents' specific disclosure, such as "optimization module" and "high priority function," be construed to cover the accused "Graph Compiler" and its process of analyzing and placing "compute-heavy layers" of a neural network?
  • A key evidentiary question will be one of algorithmic function: does the accused Graph Compiler's placement algorithm, which is described as optimizing for factors like locality and routing distance, perform the specific technical steps required by the claims? Specifically, does it choose between square and linear tile shapes based on where a function "executes optimally" (’975 Patent), or does it assign functions to tiles expressly because of the tiles' "high routing priority" under the static network policy (’968 Patent)?
  • The case will also likely feature a significant dispute regarding knowledge and intent. A central question for willfulness will be whether Plaintiff can prove that Defendant's alleged pre-suit awareness of Plaintiff's technology and diagrams establishes the requisite knowledge and deliberate or reckless disregard for Plaintiff's patent rights.