DCT

1:22-cv-01455

Seoul Semiconductor Co Ltd v. Ge Healthcare Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:22-cv-01455, D. Del., 11/04/2022
  • Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant GE Healthcare Inc. is a Delaware corporation and has allegedly committed acts of infringement in the district.
  • Core Dispute: Plaintiffs allege that Defendant’s GE Healthcare Lullaby LED Phototherapy System infringes nine patents related to the fundamental structure, composition, and fabrication of light-emitting diodes (LEDs).
  • Technical Context: The patents relate to semiconductor device architecture for LEDs, a technology critical to modern lighting, displays, and medical devices due to its efficiency, longevity, and compact size.
  • Key Procedural History: The complaint alleges that Plaintiffs’ counsel sent a letter to Defendant on October 24, 2022, notifying it of the alleged infringement and identifying several of the patents-in-suit. An inter partes review (IPR) certificate for U.S. Patent No. 7,667,225 indicates that asserted independent claim 1, among others, was found patentable in IPR2020-00146, a finding that may inform future validity disputes concerning that patent.

Case Timeline

Date Event
2008-07-08 Priority Date for U.S. Patent No. 7,982,234
2008-09-30 Priority Date for U.S. Patent No. 8,648,369
2009-03-06 Priority Date for U.S. Patent No. 7,667,225
2010-01-05 Priority Date for U.S. Patent No. 10,418,514
2010-02-23 Issue Date for U.S. Patent No. 7,667,225
2010-03-31 Priority Date for U.S. Patent No. 8,791,483
2010-09-24 Priority Date for U.S. Patent No. 9,293,664
2010-11-26 Priority Date for U.S. Patent No. 8,604,496
2011-07-19 Issue Date for U.S. Patent No. 7,982,234
2012-06-28 Priority Date for U.S. Patent No. 10,672,952
2013-12-10 Issue Date for U.S. Patent No. 8,604,496
2014-02-11 Issue Date for U.S. Patent No. 8,648,369
2014-07-29 Issue Date for U.S. Patent No. 8,791,483
2014-12-19 Priority Date for U.S. Patent No. 10,193,020
2016-03-22 Issue Date for U.S. Patent No. 9,293,664
2019-01-29 Issue Date for U.S. Patent No. 10,193,020
2019-09-17 Issue Date for U.S. Patent No. 10,418,514
2020-06-02 Issue Date for U.S. Patent No. 10,672,952
2022-10-24 Plaintiffs' counsel allegedly sent pre-suit notice letter to Defendant
2022-11-02 Defendant's counsel allegedly acknowledged receipt of notice letter
2022-11-04 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,418,514 - "Light emitting diode and method of fabricating the same," Issued September 17, 2019

The Invention Explained

  • Problem Addressed: The patent addresses performance degradation in LEDs caused by factors such as electrostatic discharge (ESD) breakdown, current concentration, and crystal defects that reduce internal quantum efficiency. (Compl. Ex. A, ’514 Patent, col. 2:1-12).
  • The Patented Solution: The invention introduces a complex layered structure between the primary n-type and p-type semiconductor layers. This structure includes a specifically designed "superlattice layer" in conjunction with an "undoped intermediate layer" and an "electron reinforcing layer" to improve crystal quality and manage electron flow, thereby enhancing device performance and reliability. (Compl. Ex. A, ’514 Patent, col. 3:36-50). The patent describes how this specific combination of layers, with controlled silicon doping only in the final layer of the superlattice, improves the LED's electrical and optical characteristics. (Compl. Ex. A, ’514 Patent, col. 5:56-6:6).
  • Technical Importance: This approach seeks to refine the internal structure of the LED at a microscopic level to overcome fundamental physical limitations on efficiency and robustness that were prevalent in high-output semiconductor lighting. (Compl. Ex. A, ’514 Patent, col. 1:47-53).

Key Claims at a Glance

  • The complaint asserts one or more claims, including exemplary dependent claim 14, which relies on independent claim 1. (Compl. ¶26).
  • The essential elements of independent claim 1 include:
    • An n-type contact layer doped with silicon.
    • A p-type contact layer.
    • An active region between the n-type and p-type contact layers.
    • A superlattice layer between the n-type contact layer and the active region, itself comprising a plurality of layers.
    • An undoped intermediate layer between the superlattice layer and the n-type contact layer.
    • An electron reinforcing layer between the undoped intermediate layer and the superlattice layer.
    • A specific doping profile wherein only the final layer of the superlattice closest to the active region is doped with silicon, and at a concentration higher than that of the n-type contact layer. (Compl. Ex. A, ’514 Patent, col. 15:6-26).
  • The complaint reserves the right to assert other claims. (Compl. ¶26).

U.S. Patent No. 8,604,496 - "Optical semiconductor device," Issued December 10, 2013

The Invention Explained

  • Problem Addressed: The patent seeks to improve the efficiency of optical semiconductor devices, such as LEDs. (Compl. Ex. B, ’496 Patent, col. 1:12-16).
  • The Patented Solution: The invention describes an architecture for the light-emitting "functional part" of an LED. This functional part contains multiple "active layers," each of which is a composite structure comprising a "multilayer stacked body" (alternating thick and thin films), an "n-side barrier layer," a "well layer," and a "p-side barrier layer." (Compl. Ex. B, ’496 Patent, Abstract). This intricate arrangement is designed to precisely control the energy landscape for electrons and holes, thereby optimizing their recombination into light within the well layer. (Compl. Ex. B, ’496 Patent, col. 2:44-53).
  • Technical Importance: This layered approach within each active region provides a sophisticated method for engineering the quantum-level behavior of the device to enhance light emission efficiency beyond what simpler structures could achieve. (Compl. Ex. B, ’496 Patent, col. 1:21-25).

Key Claims at a Glance

  • The complaint asserts one or more claims, including exemplary independent claim 1. (Compl. ¶34).
  • The essential elements of independent claim 1 include:
    • An n-type semiconductor layer.
    • A p-type semiconductor layer.
    • A functional part between the n-type and p-type layers, comprising a plurality of stacked active layers.
    • Wherein at least two of the active layers include: a multilayer stacked body with alternating thick and thin film layers; an n-side barrier layer; a well layer; and a p-side barrier layer, arranged in a specific sequence relative to the multilayer stacked body and the p-type layer. (Compl. Ex. B, ’496 Patent, col. 13:51-14:23).
  • The complaint reserves the right to assert other claims. (Compl. ¶34).

Multi-Patent Capsule: U.S. Patent No. 7,667,225 - "Light emitting device," Issued February 23, 2010

  • Technology Synopsis: The patent describes an LED with a multi-quantum well structure containing a "carrier trap portion." This portion has a band-gap energy that gradually decreases from its periphery to its center, which is intended to improve efficiency by managing electron-hole recombination. (Compl. Ex. C, ’225 Patent, Abstract).
  • Asserted Claims: Exemplary claim 1. (Compl. ¶45).
  • Accused Features: The complaint alleges that the well layers within the accused product's LED chip include indium that varies in concentration, creating regions corresponding to carrier trap portions with a related drop in band-gap energy. (Compl. ¶48).

Multi-Patent Capsule: U.S. Patent No. 10,193,020 - "Semiconductor light emitting device and method of manufacturing the same," Issued January 29, 2019

  • Technology Synopsis: The patent details a nitride semiconductor LED with a vertical structure that includes specific electrode arrangements. A key feature is a "cover metal layer" at a corner that overlaps a second electrode, along with specific relationships between electrode widths designed to improve current spreading and device performance. (Compl. Ex. D, ’020 Patent, Abstract).
  • Asserted Claims: Exemplary claim 1. (Compl. ¶53).
  • Accused Features: The complaint alleges the accused LED chip includes various structural elements such as mesa regions, a second electrode, a cover metal layer, and an insulating layer arranged in the claimed configuration. (Compl. ¶¶55, 57, 59).

Multi-Patent Capsule: U.S. Patent No. 8,791,483 - "High efficiency light emitting diode and method for fabricating the same," Issued July 29, 2014

  • Technology Synopsis: The patent discloses an LED structure built upon a support substrate. The invention includes a semiconductor stack with a first compound semiconductor layer having protrusions on its upper surface, aiming to enhance light extraction and overall efficiency. (Compl. Ex. E, ’483 Patent, Abstract).
  • Asserted Claims: Exemplary claim 1. (Compl. ¶64).
  • Accused Features: The accused LED chip is alleged to contain a support substrate and a semiconductor stack with a first compound semiconductor layer that has protrusions on its upper surface. (Compl. ¶66).

Multi-Patent Capsule: U.S. Patent No. 10,672,952 - "Light emitting diode for surface mount technology, method of manufacturing the same, and method of manufacturing light emitting diode module," Issued June 2, 2020

  • Technology Synopsis: This patent describes an LED designed for surface mounting, featuring a reflection structure configured to reflect light emitted by the light-emitting structure. The invention also includes a barrier layer structured to prevent diffusion of metal from the reflection structure. (Compl. Ex. F, ’952 Patent, Abstract).
  • Asserted Claims: Exemplary claim 1. (Compl. ¶73).
  • Accused Features: The complaint alleges the accused LED chip includes a reflection structure on a p-type semiconductor layer, an insulation layer, and a barrier layer designed to prevent metal diffusion. (Compl. ¶77).

Multi-Patent Capsule: U.S. Patent No. 9,293,664 - "Wafer-level light emitting diode package and method of fabricating the same," Issued March 22, 2016

  • Technology Synopsis: The invention relates to a wafer-level LED package designed for surface mounting without bonding wires. Key features include a plurality of contact holes that extend through upper semiconductor layers to expose a first conductive layer, and specific arrangements of electrode pads connected via these holes. (Compl. Ex. G, ’664 Patent, Abstract).
  • Asserted Claims: Exemplary claim 8. (Compl. ¶82).
  • Accused Features: The accused LED package is alleged to be bonded by surface mounting without bonding wires and to include contact holes that expose a first conductive type semiconductor layer for electrical connection. (Compl. ¶¶83, 85).

Multi-Patent Capsule: U.S. Patent No. 8,648,369 - "Light emitting device and method of fabricating the same," Issued February 11, 2014

  • Technology Synopsis: This patent describes an LED with a roughened surface on its second conductivity-type nitride semiconductor layer to improve light extraction. The structure also includes a reflective metal layer and protective metal layer disposed between the first semiconductor layer and the substrate to redirect light upwards. (Compl. Ex. H, ’369 Patent, Abstract).
  • Asserted Claims: Exemplary claim 1. (Compl. ¶92).
  • Accused Features: The accused LED chip is alleged to include a first surface of its second conductivity-type layer comprising a roughened surface, as well as a reflective metal layer and protective metal layer disposed between the first conductivity-type layer and the substrate. (Compl. ¶¶94, 98).

Multi-Patent Capsule: U.S. Patent No. 7,982,234 - "Light emitting device and method for fabricating the same," Issued July 19, 2011

  • Technology Synopsis: The invention describes a vertical-structure LED with a metal material structure disposed on the second semiconductor layer. This metal structure includes an embedded metal reflection layer to reflect light, an insulating structure at its periphery, and a substrate disposed on the metal structure. (Compl. Ex. I, ’234 Patent, Abstract).
  • Asserted Claims: Exemplary claim 1. (Compl. ¶103).
  • Accused Features: The complaint alleges the accused LED chip includes a metal material structure on its second semiconductor layer, which contains a metal reflection layer, along with a peripheral insulating structure and a substrate. (Compl. ¶107).

III. The Accused Instrumentality

Product Identification

  • The GE Healthcare Lullaby LED Phototherapy System. (Compl. ¶26).

Functionality and Market Context

  • The accused instrumentality is a medical phototherapy device that uses LEDs as its light source. (Compl. ¶27). The complaint's allegations focus not on the system's medical function, but on the microscopic physical structure of the constituent LED chips within the device. (Compl. ¶¶27-29). The complaint provides a series of images, from the overall device down to Transmission Electron Microscope (TEM) images of the LED chip's internal layers, to identify the allegedly infringing components. (Compl. ¶27). One such image depicts the LED module extracted from the device, showing five LED packages mounted on a circuit board. (Compl. ¶27). The complaint does not contain allegations regarding the product’s specific market share or commercial positioning, but identifies it as a product manufactured and sold by GE Healthcare Inc. (Compl. ¶26).

IV. Analysis of Infringement Allegations

U.S. Patent No. 10,418,514 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a light emitting diode, comprising: an n-type contact layer doped with silicon; a p-type contact layer; [and] an active region disposed between [them]... The complaint alleges the accused LED chip contains an epitaxial structure with an n-type contact layer below the active region and a p-type contact layer above the active region. A TEM image is provided to show these layers. (Compl. ¶27). ¶27, ¶28 Compl. Ex. A, col. 5:56-65
a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers... The complaint alleges the presence of layers both above and below the active region, including a spacer layer over the n-type contact layer. A TEM image shows a region of alternating thin bright layers and thick dark layers, which is alleged to constitute this structure. (Compl. ¶27). ¶27, ¶29 Compl. Ex. A, col. 6:7-13
an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer; and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer... The complaint does not explicitly identify separate layers corresponding to the "undoped intermediate layer" and "electron reinforcing layer." Instead, it refers to a "spacer layer" and a "p-type clad layer" and alleges their presence based on TEM images. The mapping of these alleged structures to the claimed elements is not explicitly detailed. (Compl. ¶29). ¶29 Compl. Ex. A, col. 5:59-6:6
wherein only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer. The complaint does not provide specific allegations or evidence regarding the silicon doping concentration profile within the alleged "spacer layer" or any other layers. The infringement allegation for this limitation appears to be based on information and belief. ¶26 Compl. Ex. A, col. 6:42-50

Identified Points of Contention:

  • Structural Mapping: A primary question will be whether the layers identified in the complaint's TEM images as a "spacer layer" and "p-type clad layer" can be shown to meet the structural and functional requirements of the claimed "superlattice layer," "undoped intermediate layer," and "electron reinforcing layer." The complaint's description of the accused device uses different terminology than the claim language, creating a potential dispute over whether the accused structure reads on the claims.
  • Evidentiary Sufficiency: The complaint provides no direct evidence, such as chemical analysis, for the specific silicon doping profile required by the final limitation of claim 1. The infringement analysis may hinge on whether Plaintiffs can produce evidence to substantiate this allegation regarding the precise material composition and doping concentration of the microscopic layers.

U.S. Patent No. 8,604,496 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
An optical semiconductor device, comprising: an n-type semiconductor layer; a p-type semiconductor layer; and a functional part provided between the n-type semiconductor layer and the p-type semiconductor layer... The complaint alleges the accused LED chip's layer structure includes, from bottom to top, an n-type semiconductor layer, a functional part, and a p-type semiconductor layer. (Compl. ¶37). ¶37 Compl. Ex. B, col. 2:44-48
the functional part including a plurality of active layers stacked in a direction from the n-type semiconductor layer toward the p-type semiconductor layer... The complaint asserts the functional part includes multiple active layers stacked in the specified direction. A TEM image is provided showing a series of stacked layers alleged to be these active layers. (Compl. ¶38). ¶38 Compl. Ex. B, col. 2:49-53
at least two of the active layers including: a multilayer stacked body including a plurality of thick film layers and a plurality of thin film layers alternately stacked in the direction... Based on a TEM image, the complaint alleges the active layers include a multilayer stacked body. It describes this body as comprising "relatively bright and thin layers (wells) separated by relatively thick dimmer layers (barriers)" that are alternately stacked. (Compl. ¶39). ¶39 Compl. Ex. B, col. 2:54-58
an n-side barrier layer provided between the multilayer stacked body and the p-type semiconductor layer; a well layer; and a p-side barrier layer provided between the well layer and the p-type semiconductor layer... The complaint alleges that "the active layer includes an n-side barrier layer provided between the multilayer stacked body and the p-type semiconductor layer, a well layer; and a p-side barrier layer provided between the well layer and the p-type semiconductor layer." (Compl. ¶40). ¶40 Compl. Ex. B, col. 2:58-65

Identified Points of Contention:

  • Technical Interpretation: An issue may arise as to whether the visual characteristics of the layers in the provided TEM images (e.g., "bright," "dim," "thick," "thin") are sufficient to establish the specific structural and compositional identities required by the claims (e.g., "well layer," "n-side barrier layer," "multilayer stacked body").
  • Scope Questions: The definition of "multilayer stacked body" and its relationship to the surrounding "n-side barrier layer" and "p-side barrier layer" may be a point of contention. The analysis will question whether the accused structure, as depicted, contains distinct components that meet each of these claimed limitations, or if the alleged layers are part of a single, undifferentiated structure.

V. Key Claim Terms for Construction

For the ’514 Patent:

  • The Term: "superlattice layer" (Claim 1)
  • Context and Importance: This term defines a core structural component of the invention. Its construction will be critical because the complaint identifies a "spacer layer" in the accused device, and the infringement case will depend on whether this alleged "spacer layer" falls within the scope of the claimed "superlattice layer" which has specific doping and structural requirements.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the superlattice layer as being formed by "alternately stacking the GaN layer and the InGaN layer," which could be read to cover various multi-layered semiconductor structures. (Compl. Ex. A, ’514 Patent, col. 6:7-9).
    • Evidence for a Narrower Interpretation: The patent repeatedly emphasizes a specific function and doping profile, stating that "only a final layer of the superlattice layer ... is doped with silicon" and that this structure improves junction characteristics. (Compl. Ex. A, ’514 Patent, col. 6:39-45). This could support a narrower construction that requires not just a layered structure, but one with this precise doping characteristic.

For the ’496 Patent:

  • The Term: "multilayer stacked body" (Claim 1)
  • Context and Importance: This term is central to defining the internal structure of the claimed "active layers." The infringement analysis hinges on whether the alternating bright and dim layers shown in the complaint's TEM images constitute this specific claimed body, which is a distinct element from the claimed "n-side" and "p-side" barrier layers. Practitioners may focus on this term to determine if the claim requires three distinct components (the body, n-side barrier, p-side barrier) or if these can be interpreted as overlapping parts of a single larger structure.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the body as including "a plurality of thick film layers and a plurality of thin film layers alternately stacked," which could potentially read on any alternating layered structure within the active region. (Compl. Ex. B, ’496 Patent, col. 2:54-57).
    • Evidence for a Narrower Interpretation: The claim language recites the "multilayer stacked body" as a distinct element from the "n-side barrier layer" and the "p-side barrier layer," suggesting it is a separate and independent component. The detailed description and figures may further define it as a specific substructure located between the n-side and p-side barrier layers, supporting a narrower reading. (Compl. Ex. B, ’496 Patent, col. 2:58-65).

VI. Other Allegations

  • Indirect Infringement: The complaint does not allege indirect infringement. The counts are limited to direct infringement under 35 U.S.C. § 271(a).
  • Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for willfulness is alleged pre-suit knowledge stemming from a notice letter sent by Plaintiffs’ counsel to Defendant’s CEO on October 24, 2022, which identified an exemplary infringing product and several of the patents-in-suit. (Compl. ¶¶ 20, 31, 42, 50, 61, 70, 79, 89, 100).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of structural correlation: can the physical layers observed in microscopic images of the accused LED, which the complaint describes with terms like "spacer layer," be proven to possess the specific compositional, structural, and functional properties required by the patent claims, which use distinct terminology such as "superlattice layer" and "multilayer stacked body"?
  • A key evidentiary question will be one of compositional proof: what evidence will be presented to demonstrate that the accused LED chip contains the precise doping profiles and material compositions (e.g., silicon concentration gradients, indium content variation) required by several of the asserted claims, allegations for which the complaint relies on TEM images and general assertions rather than specific chemical analysis?
  • A central legal question will be one of claim construction: how will the court define key structural terms like "superlattice layer" and "multilayer stacked body" in the context of their surrounding elements? The resolution of whether these terms denote functionally and structurally distinct components or can be read more broadly will be critical to the infringement analysis.