DCT

3:22-cv-02001

Greenthread LLC v. Intel Corp

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:22-cv-00105, W.D. Tex., 04/29/2022
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendants have regular and established places of business in the district, have committed acts of infringement in the district, and reside in the district.
  • Core Dispute: Plaintiff alleges that Defendants’ semiconductor devices, including CPUs, flash memory, and image sensors, and the electronic products incorporating them (e.g., laptops and computers), infringe six patents related to semiconductor structures with graded dopant regions.
  • Technical Context: The technology concerns methods of manufacturing semiconductors with specific arrangements of chemical impurities (dopants) to create electric fields that improve charge carrier movement, thereby increasing device speed, efficiency, and reliability.
  • Key Procedural History: The complaint does not mention any prior litigation, IPR proceedings, or licensing history related to the patents-in-suit. The patents were assigned from the inventor, Dr. G.R. Mohan Rao, to Greenthread, LLC.

Case Timeline

Date Event
2004-09-03 Patent Priority Date for all patents-in-suit
2013-04-16 U.S. Patent No. 8,421,195 Issued
2015-11-17 U.S. Patent No. 9,190,502 Issued
2019-12-17 U.S. Patent No. 10,510,842 Issued
2020-08-04 U.S. Patent No. 10,734,481 Issued
2021-09-14 U.S. Patent No. 11,121,222 Issued
2022-04-26 U.S. Patent No. 11,316,014 Issued
2022-04-29 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,421,195: Semiconductor Devices with Graded Dopant Regions (Issued Apr. 16, 2013)

The Invention Explained

  • Problem Addressed: The patent addresses performance limitations in semiconductor devices caused by the movement of charge carriers (electrons and holes). In devices like Bipolar Junction Transistors (BJTs), performance is limited by the speed of carrier transit, while in devices like DRAMs and image sensors, unwanted minority carriers can cause errors, such as reducing data retention time or creating "dark current" that degrades image quality (’195 Patent, col. 1:24-38, col. 2:61-67).
  • The Patented Solution: The invention introduces a "graded dopant region"—a layer within the semiconductor where the concentration of impurities is intentionally varied with depth. This gradient creates a built-in electric "drift field" that actively pushes or pulls charge carriers in a desired direction. This can be used to sweep unwanted minority carriers away from sensitive areas or to accelerate the movement of desired carriers, thereby improving device speed and reliability (’195 Patent, col. 2:34-45, Fig. 5B).
  • Technical Importance: This approach provides a method for actively managing charge carriers within the bulk silicon, offering a potential improvement over conventional designs that rely on uniform doping and passive carrier diffusion, particularly as device dimensions shrink and parasitic effects become more pronounced (’195 Patent, col. 1:49-56).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2, 3, 5, and 6 (Compl. Ex. 8, p. 148).
  • Independent Claim 1 elements include:
    • A CMOS semiconductor device
    • Comprising a surface layer and a substrate
    • An active region with a source and drain on the surface layer
    • A single drift layer between the surface layer and substrate, with a graded concentration of dopants creating a first static unidirectional electric drift field to aid minority carrier movement
    • At least one well region disposed in the drift layer, also having a graded dopant concentration creating a second static unidirectional electric drift field

U.S. Patent No. 9,190,502: Semiconductor Devices with Graded Dopant Regions (Issued Nov. 17, 2015)

The Invention Explained

  • Problem Addressed: This patent, part of the same family, addresses similar problems of managing charge carriers to improve performance across various semiconductor devices, including logic, memory, and sensors (’502 Patent, col. 1:28-40).
  • The Patented Solution: The ’502 Patent also describes using a graded dopant concentration in a "drift layer" to create an electric field. The claims focus on the use of this structure to aid the movement of minority carriers either from the substrate to the surface layer or from the surface layer to the substrate, and the application of a second, similar field within a "well region" (’502 Patent, col. 4:8-27). This dual-field structure provides targeted control over carrier movement.
  • Technical Importance: The technology provides a flexible semiconductor architecture that can be adapted to either sweep away unwanted carriers (improving DRAM refresh and image sensor quality) or accelerate desired carriers (improving transistor switching speed), depending on the direction of the engineered electric fields (’502 Patent, Abstract).

Key Claims at a Glance

  • The complaint asserts independent claim 7 and dependent claims 8, 9, and 11 (Compl. Ex. 8, p. 148).
  • Independent Claim 7 elements include:
    • A semiconductor device
    • Comprising a surface layer and a substrate
    • An active region with a source and drain on the surface layer
    • A single drift layer with a graded dopant concentration generating a first static unidirectional electric drift field
    • At least one well region in the drift layer with a graded dopant concentration generating a second static unidirectional electric drift field

Multi-Patent Capsule: U.S. Patent No. 10,510,842

  • Patent Identification: U.S. Patent No. 10,510,842, "Semiconductor Devices with Graded Dopant Regions," issued Dec. 17, 2019.
  • Technology Synopsis: This patent continues the theme of using graded dopant regions to improve semiconductor device performance. The claims focus on a device structure with at least two separate "active regions" (where transistors can be formed) that both have a graded dopant portion to aid carrier movement from the device surface towards the substrate (’842 Patent, col. 4:26-40).
  • Asserted Claims: Independent claims 1 and 9 are asserted (Compl. Ex. 8, p. 148).
  • Accused Features: The complaint alleges that Intel CPUs, Intel/Micron/WD flash memories, and Sony image sensors, along with Dell products containing them, have the claimed multi-active region structure with graded dopants (Compl. ¶¶101-102).

Multi-Patent Capsule: U.S. Patent No. 10,734,481

  • Patent Identification: U.S. Patent No. 10,734,481, "Semiconductor Devices with Graded Dopant Regions," issued Aug. 4, 2020.
  • Technology Synopsis: This patent claims a semiconductor device with multiple active regions and graded dopants, further specifying "at least one well region adjacent to the first or second active region containing at least one graded dopant region" to aid carrier movement from the surface to the substrate (’481 Patent, col. 5:1-6).
  • Asserted Claims: Independent claims 1 and 20 are asserted (Compl. Ex. 8, p. 148).
  • Accused Features: The complaint alleges infringement by Intel CPUs, Intel/Micron/WD flash memories, and Sony image sensors, and the Dell products incorporating them, based on their alleged use of graded dopants in both active regions and adjacent well regions (Compl. ¶¶109-110).

Multi-Patent Capsule: U.S. Patent No. 11,121,222

  • Patent Identification: U.S. Patent No. 11,121,222, "Semiconductor Devices with Graded Dopant Regions," issued Sep. 14, 2021.
  • Technology Synopsis: This patent claims a Very Large Scale Integration (VLSI) semiconductor device specifically. It requires graded dopant regions that aid carrier movement towards an area of the substrate "where there are no active regions," and further requires that at least some of the transistors form the device's "digital logic" (’222 Patent, col. 4:32-51).
  • Asserted Claims: Independent claims 1, 21, 39, 41, 42, and 44 are asserted (Compl. Ex. 8, p. 148).
  • Accused Features: The complaint accuses Intel CPUs, Intel/Micron/WD flash memories, and Sony image sensors, and Dell products containing them, of being VLSI devices that use graded dopants to move carriers away from active logic areas (Compl. ¶¶117-118).

Multi-Patent Capsule: U.S. Patent No. 11,316,014

  • Patent Identification: U.S. Patent No. 11,316,014, "Semiconductor Devices with Graded Dopant Regions," issued Apr. 26, 2022.
  • Technology Synopsis: This patent is directed to an "electronic system" comprising at least one semiconductor device with the graded dopant architecture. The claims recite a system-level invention that incorporates a device with multiple active regions, graded dopants, and well regions where transistors form digital logic (’014 Patent, col. 5:48-67).
  • Asserted Claims: Independent claims 1 and 21 are asserted (Compl. Ex. 8, p. 148).
  • Accused Features: The complaint alleges that Dell computing products incorporating infringing Intel, Micron, WD, or Sony semiconductor components constitute the claimed "electronic system" (Compl. ¶¶125-126).

III. The Accused Instrumentality

  • Product Identification: The accused instrumentalities are broadly defined as semiconductor devices and the electronic products containing them (Compl. ¶2.a-b). Specific exemplary products identified include Intel’s 10th (“Comet Lake”), 11th (“Tiger Lake”), and 12th (“Alder Lake”) generation CPUs, such as the Intel Core i7 11800H (Compl. ¶50). Also accused are flash memory products from Intel, Micron, and Western Digital/SanDisk, and image sensors from Sony (Compl. ¶¶54, 64, 70, 76). Dell products such as the Alienware M15 R6 laptop are accused of infringing by incorporating these components (Compl. ¶19, ¶62).
  • Functionality and Market Context: The complaint alleges these components are fundamental to modern electronics (Compl. ¶1). The accused CPUs are high-performance processors for computers, while the flash memory and image sensors are used in storage devices and cameras, respectively. The complaint highlights that Dell is an authorized "System Manufacturer" for Intel and incorporates the accused Intel components into its widely sold computer products (Compl. ¶14). The infringement contentions provide detailed technical analysis of the accused components, including a cross-sectional scanning electron microscope (SEM) image of the Intel CPU's L2 cache, which is alleged to contain the infringing structures (Compl. Ex. 9, p. 179). Another visual shows a screenshot from Dell's website listing numerous Dell PCs that incorporate accused Micron SSDs (Compl. ¶68).

IV. Analysis of Infringement Allegations

The complaint incorporates by reference detailed preliminary infringement contentions, including claim charts with technical analysis of exemplary products (Compl. ¶18, Exs. 9-12). The following charts summarize the allegations against the exemplary Intel Core i7 11800H CPU.

  • ’195 Patent Infringement Allegations
Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a surface layer; The top portion of the semiconductor die where transistors are fabricated. Ex. 9, p. 227 col. 3:56-61
a substrate; The underlying silicon wafer of the semiconductor die, which analysis shows is p-type doped. Ex. 9, p. 226 col. 4:19-20
an active region including a source and a drain, disposed on one surface of said surface layer; The area within the silicon containing the source and drain terminals of the transistors (e.g., FinFETs). Ex. 9, p. 227 col. 4:21-23
a single drift layer disposed between the other surface of said surface layer and said substrate, said drift layer having a graded concentration of dopants... having a first static unidirectional electric drift field... A region beneath the active transistors where the dopant concentration is varied with depth, creating an electric field. This is evidenced by Spreading Resistance Profiling (SRP) and Secondary Ion Mass Spectrometry (SIMS) data showing a changing dopant concentration versus depth. Ex. 9, pp. 226-227 col. 4:24-32
at least one well region disposed in said single drift layer, said well region having a graded concentration of dopants and a second static unidirectional electric drift field... P-wells and N-wells within the drift layer that also exhibit a graded dopant concentration, creating a second electric field. SIMS data allegedly shows graded concentrations of both boron (p-type) and phosphorus (n-type) dopants. Ex. 9, p. 227 col. 4:33-40
  • ’502 Patent Infringement Allegations
Claim Element (from Independent Claim 7) Alleged Infringing Functionality Complaint Citation Patent Citation
a surface layer; The top portion of the semiconductor die. Ex. 9, p. 229 col. 4:9
a substrate; The underlying silicon wafer of the die. Ex. 9, p. 229 col. 4:10
an active region including a source and a drain, disposed on one surface of said surface layer; The area containing the source/drain terminals of transistors. Ex. 9, p. 229 col. 4:11-13
a single drift layer... having a graded concentration of dopants generating a first static unidirectional electric drift field to aid the movement of minority carriers from said surface layer to said substrate; The region beneath the active transistors with a graded dopant profile, which is alleged to create an electric field that sweeps minority carriers down into the substrate. Ex. 9, p. 229 col. 4:14-20
and at least one well region disposed in said single drift layer... having a graded concentration of dopants generating a second static unidirectional electric drift field to aid the movement of minority carriers from said surface layer to said substrate. Well regions within the drift layer that also have a graded dopant profile, creating a second, localized electric field that also sweeps minority carriers down into the substrate. Ex. 9, p. 230 col. 4:21-27
  • Identified Points of Contention:
    • Scope Questions: The patents describe relatively simple planar structures, while the accused products utilize advanced three-dimensional FinFET transistor architectures. A central question may be whether the claimed elements, such as "a single drift layer" and "an active region... on one surface," can be read to cover the complex, multi-layered topography of a modern CPU manufactured on a 10nm process node. The infringement contentions rely on SEM cross-section images to map these elements, as seen in an image from Exhibit 9 showing the alleged substrate and first surface of an Intel L2 cache sample (Compl. Ex. 9, p. 179).
    • Technical Questions: The infringement allegations rely heavily on analytical techniques like SIMS and SRP to demonstrate the "graded dopant concentration" (Compl. Ex. 9, p. 190). A key factual dispute may arise over the interpretation of this data. For instance, questions may be raised as to whether the observed variations in dopant concentration are intentional "graded" regions designed to create the claimed "drift field," or if they are merely inherent artifacts of the complex doping and annealing processes used in modern semiconductor manufacturing that do not perform the claimed function.

V. Key Claim Terms for Construction

  • The Term: "graded dopant concentration"

  • Context and Importance: This term is the central inventive concept of all asserted patents. Its definition will be critical to the infringement analysis, as the dispute will likely focus on whether the dopant profiles in the accused devices meet this limitation. Practitioners may focus on this term because its scope will determine whether naturally occurring gradients from manufacturing processes fall within the claims or if an intentionally engineered profile is required.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The independent claims do not specify the shape of the gradient. Dependent claims in the family recite specific profiles (e.g., "quasi-linear," "exponential," "complimentary error function") (’195 Patent, claims 5-7). The doctrine of claim differentiation may suggest that the independent claim is not limited to any specific gradient shape and could be construed more broadly.
    • Evidence for a Narrower Interpretation: The specification repeatedly describes the purpose of the gradient as creating an "aiding drift electric field" to "enhance the diffusing minority carrier's speed" or "sweep these unwanted minority carriers" (’195 Patent, col. 1:53-56, col. 3:58-61). A defendant may argue that the term should be limited to gradients that are intentionally designed and sufficiently steep to produce a functionally significant electric field for aiding carrier movement, as opposed to any incidental variation in doping.

  • The Term: "a single drift layer"

  • Context and Importance: The claims consistently recite "a single drift layer" in which other structures like "well regions" are disposed. This term is critical because modern CPUs have numerous, complex, inter-diffused layers. Whether this complex structure can be characterized as containing "a single drift layer" will be a key point of contention.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The patents do not define the precise boundaries or composition of the "drift layer," suggesting it is a functional region defined by the presence of the graded dopant concentration. Plaintiff may argue that as long as a single, contiguous region with a functional gradient can be identified in the accused device, this limitation is met.
    • Evidence for a Narrower Interpretation: The patent figures, such as Figure 4 of the ’195 patent, depict the drift layer as a distinct, unitary region (the "n- epitaxial drift region"). A defendant may argue that this term requires a structurally distinct and intentionally formed layer, and that the highly complex, multi-layered structure of a FinFET device, with its fins, gates, and source/drain regions, cannot be fairly characterized as having "a single drift layer."

VI. Other Allegations

  • Indirect Infringement: The complaint does not contain counts for indirect infringement (inducement or contributory infringement). The factual allegations focus on direct infringement by making, using, and selling the accused products (Compl. ¶¶ 49, 63, 73).
  • Willful Infringement: The complaint does not allege facts that would typically support a claim for willful infringement, such as pre-suit knowledge of the patents or egregious conduct. The prayer for relief requests a finding that the case is exceptional under 35 U.S.C. § 285, but the factual basis for this request is not developed in the complaint (Compl. p. 27, ¶D).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of structural correspondence: can the claim language and diagrams, which depict relatively discrete semiconductor layers (e.g., "a single drift layer," "a surface layer"), be mapped onto the complex, three-dimensional, and inter-diffused structures of modern FinFET-based CPUs? The case may turn on whether the plaintiff can prove, through expert testimony and analysis of evidence like the SEM images provided, that the claimed structures are present in the accused devices.
  • A key technical question will be one of functional intent: does the analytical data (SIMS, SRP) from the accused devices show dopant gradients that are intentionally engineered to create the claimed "unidirectional electric drift field" for carrier management, or are these gradients incidental artifacts of the manufacturing process that do not perform the claimed function in the manner disclosed by the patents?
  • A central question of claim scope will be the construction of "graded dopant concentration." The outcome of this construction will likely determine whether a broad range of doping profiles infringe or only those with specific, functionally-defined characteristics, significantly impacting the number of accused products that fall within the scope of the patents.