DCT
3:23-cv-00113
BeSang Inc v. Intel Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: BeSang Inc. (Oregon)
- Defendant: Intel Corporation (Delaware)
- Plaintiff’s Counsel: Chernoff Vilhauer LLP; Caldwell Cassady & Curry P.C.
- Case Identification: 3:23-cv-00113, D. Or., 01/23/2023
- Venue Allegations: Plaintiff alleges venue is proper in the District of Oregon because Intel has committed acts of infringement in the district and maintains regular and established places of business there, including its primary semiconductor design, development, and production facilities in Hillsboro, Oregon.
- Core Dispute: Plaintiff alleges that Defendant’s 3D NAND flash memory products, which utilize a "CMOS under array" architecture, infringe a patent related to vertical memory device structures.
- Technical Context: The technology concerns three-dimensional (3D) semiconductor memory, an approach that increases data storage density by stacking memory cells vertically, overcoming the physical scaling limitations of traditional two-dimensional (2D) planar memory.
- Key Procedural History: The complaint alleges a significant pre-suit history between the parties. This includes allegations that Intel personnel attended technical presentations by the patent’s inventor, that the parties engaged in collaboration and licensing discussions regarding the patented technology, and that Intel cited the patent-in-suit’s family during the prosecution of its own patents. These allegations may be intended to support claims of pre-suit knowledge for willfulness.
Case Timeline
| Date | Event |
|---|---|
| 2003-01-01 | BeSang Inc. is incorporated to develop 3D integrated circuits. |
| 2004-06-21 | '702 Patent Priority Date. |
| 2004-09-03 | Application for '702 Patent filed. |
| 2008-05-27 | '702 Patent issued by the USPTO. |
| 2010-05-01 | BeSang inventor presents on 3D IC architecture at IEEE workshop attended by Intel. |
| 2012-05-01 | BeSang inventor makes another presentation at IEEE workshop attended by Intel. |
| 2014-06-01 | BeSang and Intel engage in discussions about BeSang's 3D technology. |
| 2015-03-26 | Intel announces its first 3D NAND flash memory technology. |
| 2016-11-24 | Intel's SSD 600p Series, an accused product, is launched. |
| 2017-01-01 | BeSang proposes a license agreement to Intel, which is refused. |
| 2020-02-03 | Intel discloses '702 Patent's application in an IDS for its own patent application. |
| 2022-07-07 | Intel again discloses '702 Patent's application in an IDS. |
| 2023-01-23 | Complaint filed. |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,378,702 - “Vertical Memory Device Structures,” issued May 27, 2008
The Invention Explained
- Problem Addressed: The patent's background section describes the challenge that as semiconductor devices became smaller, the manufacturing equipment and technologies required to support further size reduction became increasingly expensive, indicating that conventional 2D device scaling was reaching its practical limits (Compl. ¶16; ’702 Patent, col. 1:33-41).
- The Patented Solution: The invention proposes a three-dimensional architecture that separates logic circuitry from memory cells. It describes forming a "stackable add-on layer" containing vertically oriented memory cells and bonding this layer onto a conventional substrate that already contains the necessary logic circuits (e.g., sense amplifiers and selectors) (’702 Patent, Abstract; col. 5:60-63). This vertical stacking, illustrated in Figure 1, allows for increased circuit density without necessarily shrinking the lateral dimensions of the components (’702 Patent, Fig. 1; Compl. ¶18).
- Technical Importance: This method provided a potential solution to the industry-wide problem of memory scaling by shifting the paradigm from horizontal shrinkage to vertical integration, thereby enabling higher memory capacity in a smaller footprint (Compl. ¶11-12).
Key Claims at a Glance
- The complaint asserts independent claim 13 (’702 Patent, col. 12:24-34; Compl. ¶43).
- The essential elements of independent claim 13 are:
- A substrate having electrical devices formed therein, and further having a dielectric layer disposed above the electrical devices;
- A stackable add-on layer having a plurality of vertically oriented semiconductor memory cells;
- The stackable add-on layer being bonded to the dielectric layer; and
- Wherein the memory cells are nonvolatile memory cells having at least one transistor.
- The complaint reserves the right to assert additional claims at a later stage (Compl. ¶38).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are Intel’s 3D NAND flash memory products, including its 32-layer, 64-layer, 96-layer, 128-layer, and 144-layer memory chips, and the various Solid-State Drives (SSDs) that incorporate these chips (Compl. ¶25, fn. 11). The Intel SSD 670p Series product is identified as being representative of all accused products (Compl. ¶52).
Functionality and Market Context
- The complaint alleges that the accused products utilize a "CMOS under array" (CuA) architecture, which involves placing the CMOS control circuits underneath the vertically stacked memory array (Compl. ¶33, 48). This structure is alleged to reduce die sizes, lower costs, and improve performance compared to competing approaches (Compl. ¶33). A marketing slide from an Intel presentation illustrates the generational progression of this CuA technology, showing increasingly dense vertical stacking from 2016 to 2020 (Compl. p. 15).
IV. Analysis of Infringement Allegations
'702 Patent Infringement Allegations
| Claim Element (from Independent Claim 13) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a substrate having electrical devices formed therein... | The accused products allegedly contain a substrate with CMOS logic circuits formed within it. A cross-section micrograph provided in the complaint purports to show these CMOS circuits (annotated in red) within the substrate (annotated in yellow) (Compl. p. 18). | ¶55, ¶56 | col. 5:60-63 |
| ...and further having a dielectric layer disposed above the electrical devices | The accused products are alleged to have a dielectric layer positioned on top of the underlying CMOS circuits. A micrograph shows this dielectric layer (annotated in green) disposed above the CMOS circuits (annotated in red) (Compl. p. 19). | ¶57, ¶58 | col. 5:35-37 |
| a stackable add-on layer having a plurality of vertically oriented semiconductor memory cells | The products allegedly contain an array of vertically oriented, nonvolatile memory cells. An Intel marketing video is cited to show how multiple layers of memory cells are "stacked up" to create more density (Compl. p. 21). | ¶60, ¶61, ¶63 | col. 10:50-58 |
| the stackable add-on layer being bonded to the dielectric layer | The complaint alleges the memory array is bonded to the underlying dielectric layer. A micrograph is presented with annotations to show the memory array (blue) bonded to the dielectric layer (orange) through a conductive plane (red) (Compl. p. 22). | ¶64, ¶65 | col. 10:59-62 |
| wherein the memory cells are nonvolatile memory cells having at least one transistor | The memory cells in the accused products are described as NAND cells, which are nonvolatile, and allegedly include at least one transistor, such as a select gate source transistor. A micrograph purports to show such a transistor (annotated in light green) (Compl. p. 23). | ¶66, ¶67, ¶68 | col. 7:25-27 |
Identified Points of Contention
- Scope Questions: The infringement analysis may focus on the meaning of "stackable add-on layer" and whether it is "bonded to" the dielectric layer. The patent specification describes a process of creating this layer by cleaving it from one wafer and bonding it to another (’702 Patent, col. 4:49-54). A central question may be whether this language limits the claims to a specific layer-transfer manufacturing process, or if the terms are broad enough to read on monolithic fabrication techniques that achieve a similar final "CMOS under array" structure.
- Technical Questions: The complaint's infringement allegations rely in part on Intel's marketing materials, high-level diagrams, and annotated micrographs (e.g., Compl. pp. 13-15, 17-23). A key question for the court will be what evidence confirms that the actual, physical construction and manufacturing process of the accused products align with the specific limitations of claim 13, particularly the concepts of an "add-on layer" and the "bonding" process.
V. Key Claim Terms for Construction
The Term: "stackable add-on layer"
- Context and Importance: This term is central to the claimed invention. Its construction will likely determine whether Intel’s "CMOS under array" architecture, as manufactured, falls within the scope of the claims. Practitioners may focus on this term because the dispute could turn on whether Intel's process involves "adding" a distinct layer, as the patent arguably describes, or building the structure monolithically.
- Intrinsic Evidence for a Broader Interpretation: The patent’s summary states that memory cells "are added to the separately fabricated substrate as a thin layer" (’702 Patent, col. 2:58-60). A party could argue this is exemplary language and that the term should be understood more broadly to cover any architecture where a memory layer is functionally "added on" top of a logic substrate.
- Intrinsic Evidence for a Narrower Interpretation: The detailed description provides a more specific context, defining an "SOI layer" as a "single crystal portion of a semiconductor wafer that can be cleaved and bonded to another previously fabricated wafer" (’702 Patent, col. 4:49-52). This repeated reference to a specific wafer-cleaving and bonding process could be used to argue for a narrower construction limited to such layer-transfer methods.
The Term: "bonded to"
- Context and Importance: This term, used in conjunction with "stackable add-on layer," is critical for defining the required method of attachment between the memory and logic layers. The interpretation of "bonded" will be key to the infringement analysis.
- Intrinsic Evidence for a Broader Interpretation: A party might argue that "bonded" should be given its plain and ordinary meaning of being joined or fastened, which could encompass a variety of semiconductor fabrication techniques that create a permanent connection between layers.
- Intrinsic Evidence for a Narrower Interpretation: The patent consistently uses the term in the context of connecting a transferred SOI layer to a substrate (e.g., '702 Patent, col. 5:19-21, "the stackable add-on layer are stacked and bonded to each other"). This consistent usage could support an argument that "bonded" refers specifically to a wafer-bonding process, as distinct from layer deposition or other forms of monolithic integration.
VI. Other Allegations
Indirect Infringement
- The complaint alleges induced infringement under 35 U.S.C. § 271(b) (Compl. ¶71). The factual basis for inducement is Intel's alleged provision of "specifications, datasheets, instruction manuals, support materials, developer materials, marketing materials, and user guide materials" that allegedly instruct customers, manufacturers, and end-users to make, use, and operate the accused products in an infringing manner (Compl. ¶73).
Willful Infringement
- The complaint alleges willful infringement, asserting that Intel had pre-suit knowledge of the ’702 Patent or was willfully blind to its infringement (Compl. ¶35, 75). The allegations supporting pre-suit knowledge include: (1) Intel’s citation of the ’702 Patent family during its own patent prosecution (Compl. ¶24); (2) Intel employees’ attendance at technical workshops where the inventor presented on the technology (Compl. ¶27); and (3) direct business and licensing discussions between BeSang and Intel regarding the technology (Compl. ¶28-29, 34).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the claim terms "stackable add-on layer" and "bonded to," which are described in the patent specification in the context of a wafer-transfer process, be construed broadly enough to cover the manufacturing methods used by Intel to create its "CMOS under array" 3D NAND architecture?
- A second central issue will be evidentiary and factual: what level of pre-suit knowledge did Intel possess regarding the ’702 Patent and its potential infringement? The resolution of this question, based on the alleged history of technical presentations, direct business dealings, and patent prosecution citations, will be determinative for the claim of willful infringement and any potential for enhanced damages.