Godo Kaisha IP Bridge 1 v. Xilinx Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Godo Kaisha IP Bridge 1 (Japanese corporation)
  • Defendant: Xilinx, Inc. (Delaware corporation)
  • Plaintiff’s Counsel: Shore Chan DePumpo LLP; Ohashi & Horn LLP
• Case Identification: 2:17-cv-00100, E.D. Tex., 01/31/2017
• Venue Allegations: Plaintiff alleges venue is proper based on Defendant maintaining a regional sales office and conducting business operations in the district, purposefully placing products into the stream of commerce expected to be used in the district, and maintaining interactive commercial websites accessible to residents of the district.
• Core Dispute: Plaintiff alleges that Defendant’s Field-Programmable Gate Array (FPGA) semiconductor devices, manufactured using 28nm and 40nm processes, infringe patents related to semiconductor structure and fabrication.
• Technical Context: The patents address methods for improving semiconductor performance and reliability, specifically by managing internal mechanical stress to increase transistor speed and by altering interconnect structures to reduce electrical resistance.
• Key Procedural History: The complaint alleges that Defendant had knowledge of both patents-in-suit no later than September 21, 2016, the date of a meeting where Plaintiff provided specific notice of infringement. This date is foundational to the allegations of willful infringement.

Case Timeline

Date	Event
2003-06-16	U.S. Patent No. 7,893,501 Priority Date
2003-09-09	U.S. Patent No. 7,265,450 Priority Date
2007-09-04	U.S. Patent No. 7,265,450 Issued
2011-02-22	U.S. Patent No. 7,893,501 Issued
2016-09-21	Plaintiff allegedly provides Defendant with notice of infringement
2017-01-31	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,893,501 - "Semiconductor Device Including MISFET Having Internal Stress Film,"

• Patent Identification: U.S. Patent No. 7,893,501, "Semiconductor Device Including MISFET Having Internal Stress Film," issued February 22, 2011.

The Invention Explained

• Problem Addressed: The patent seeks to increase the operational speed of transistors (MISFETs) by enhancing the mobility of charge carriers (electrons or holes) within the semiconductor's channel region. Conventional methods required external devices to apply mechanical stress, which was impractical for integrated circuits. (’501 Patent, col. 1:15-44).
• The Patented Solution: The invention uses an "internal stress film" (e.g., a silicon nitride film) deposited directly over the source and drain regions of the transistor. This film inherently possesses a mechanical stress (either tensile or compressive) that is transferred to the transistor's channel, altering the crystal lattice and thereby increasing carrier mobility without any external apparatus. (’501 Patent, Abstract; col. 2:1-9). The specific geometry of the film relative to the gate electrode is a key aspect of the described embodiments (’501 Patent, Fig. 1).
• Technical Importance: This approach allows for localized stress engineering within a standard CMOS fabrication process, enabling the performance of n-type and p-type transistors to be independently optimized on the same chip. (’501 Patent, col. 2:21-34).

Key Claims at a Glance

• The complaint asserts independent claim 1. (Compl. ¶15).
• Essential elements of Claim 1 include:
  • A MISFET comprising an active region, a gate insulating film, a gate electrode, and source/drain regions.
  • A silicon nitride film formed over from side surfaces of the gate electrode to upper surfaces of the source/drain regions.
  • The silicon nitride film is not formed on an upper surface of the gate electrode.
  • The gate electrode protrudes upward from a surface level of parts of the silicon nitride film located at both side surfaces of the gate electrode.
• The complaint also asserts dependent claims 5-7, 10, 11, 15-19, 21, and 23-25. (Compl. ¶15).

U.S. Patent No. 7,265,450 - "Semiconductor Device and Method for Fabricating the Same,"

• Patent Identification: U.S. Patent No. 7,265,450, "Semiconductor Device and Method for Fabricating the Same," issued September 4, 2007.

The Invention Explained

• Problem Addressed: In advanced semiconductors using copper interconnects, the "damascene" fabrication process can lead to the formation of microscopic voids. When these voids concentrate at the critical interface between a lower metal interconnect and an upper connecting plug, they can significantly increase electrical resistance and degrade device reliability. (’450 Patent, col. 2:21-30).
• The Patented Solution: The patent proposes creating non-flat, textured surfaces—specifically, "convex or concave portions"—on the bottom and/or side surfaces of the trench in which the lower interconnect is formed. These geometric features act as "getters," trapping voids away from the electrically critical contact area, thereby preventing an increase in contact resistance. (’450 Patent, Abstract; col. 2:51-61). The patent describes methods for forming these features using etching masks or multi-layer dielectric films. (’450 Patent, col. 6:36-50; col. 11:21-32).
• Technical Importance: This technique provides a structural solution to a materials science problem (electromigration and void formation), improving the reliability and performance of multi-layer copper interconnects, a foundational technology for modern integrated circuits. (’450 Patent, col. 2:41-49).

Key Claims at a Glance

• The complaint asserts independent claim 1. (Compl. ¶24).
• Essential elements of Claim 1 include:
  • A substrate provided with a semiconductor element.
  • A first interlayer dielectric film provided on the substrate.
  • A first interconnect groove provided in the first interlayer dielectric film.
  • A first interconnect provided within the first interconnect groove and having convex or concave portions at least at one of its side surfaces and bottom surface.
  • A second interlayer dielectric film provided over the first interlayer dielectric film and the first interconnect.
  • A first plug that passes through the second interlayer dielectric film and comes into contact with a part of the first interconnect.
• The complaint also asserts dependent claims 2, 3, 8, 10, 11, 13, and 14. (Compl. ¶24).

III. The Accused Instrumentality

Product Identification

• The accused instrumentalities include, but are not limited to, the "Kintex-7 28nm FPGA family," the "Virtex-6 40nm FPGA device families," and more broadly, "all Xilinx devices employing Xilinx's 28nm technology and all devices employing the 40nm technology." (Compl. ¶15, ¶24).

Functionality and Market Context

• The complaint identifies the accused products as programmable semiconductor devices (FPGAs). (Compl. ¶15, ¶24). The infringement allegations focus on the underlying physical structure of the transistors and interconnects within these devices, which are fabricated at the 40nm and 28nm technology nodes, rather than the programmable logic functions they perform for end-users. (Compl. ¶15, ¶24). The complaint alleges these devices "perform substantially the same function in substantially the same way to achieve substantially the same result" as the patented inventions. (Compl. ¶15, ¶24).

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits (Exhibits B and D) that were not provided with the complaint itself; therefore, the infringement allegations are summarized below based on the narrative descriptions in the complaint. No probative visual evidence provided in complaint.

'501 Patent Infringement Allegations

The complaint alleges that the accused 28nm Xilinx devices infringe at least Claim 1 of the ’501 Patent because they include a MISFET structure that meets each limitation of the claim. (Compl. ¶15). The core of the allegation is that the accused devices contain a silicon nitride film formed over the source/drain regions but not on top of the gate electrode, and that the gate electrode protrudes upward from the level of this film, mirroring the structure claimed in the patent. (Compl. ¶15).

'450 Patent Infringement Allegations

The complaint alleges that the accused 28nm and 40nm Xilinx devices infringe at least Claim 1 of the ’450 Patent because they contain the claimed multi-layer interconnect structure. (Compl. ¶24). The allegation posits that the accused devices have a first interconnect situated within a groove that has "convex or concave portions," which is then connected to a plug from a higher layer. (Compl. ¶24).

Identified Points of Contention:

• ’501 Patent - Structural Conformance: A primary question will be evidentiary: can the plaintiff demonstrate that the accused devices’ transistors possess the highly specific three-dimensional geometry required by Claim 1? The analysis will focus on whether the silicon nitride film is truly absent from the upper surface of the gate electrode and whether the gate electrode "protrudes upward" from the film in the manner defined by the patent's specification and figures.
• ’450 Patent - Technical Scope: The dispute may center on the definition of "convex or concave portions." A key question is whether this term requires structures intentionally fabricated for the purpose of gettering voids, as taught in the patent, or if it can be construed to read on any surface irregularities that may be incidental byproducts of the defendant's 28nm or 40nm manufacturing processes.

V. Key Claim Terms for Construction

For the ’501 Patent:

• The Term: "the gate electrode protrudes upward from a surface level of parts of the silicon nitride film located at both side surfaces of the gate electrode"
• Context and Importance: This limitation defines the specific physical relationship between the gate and the stress-inducing film, which is central to the claimed structure. Practitioners may focus on this term because the infringement analysis will depend on whether the accused devices, manufactured with a different process, exhibit this precise geometric arrangement.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party might argue the term simply requires the top surface of the gate electrode to be vertically higher than the top surface of the adjacent silicon nitride film, without a specific required height difference or shape. (Compl. ¶15).
  • Evidence for a Narrower Interpretation: A party could point to the specification and Figure 1, which illustrates a distinct step-like structure, to argue the term requires a specific, significant height difference that is a direct result of the described fabrication process where the film is formed after the gate electrode. (’501 Patent, Fig. 1; col. 15:50-58).

For the ’450 Patent:

• The Term: "convex or concave portions"
• Context and Importance: This term is the central novel feature of the claimed interconnect structure. Its construction will determine whether the accused devices, which may have non-flat surfaces for various reasons, fall within the scope of the claims.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party could argue that any deviation from a perfectly flat surface on the bottom or sides of the interconnect groove, regardless of its origin or function, meets the literal language of the claim. (Compl. ¶24).
  • Evidence for a Narrower Interpretation: A party would likely argue that, read in light of the specification, the term is not merely descriptive of any shape but is a functional limitation. The patent repeatedly ties these "portions" to the object of gettering voids to solve a specific problem of contact resistance. (’450 Patent, col. 2:31-49, col. 2:57-61). The embodiments show these portions being intentionally formed through specific etching or deposition steps. (’450 Patent, col. 6:36-50).

VI. Other Allegations

• Indirect Infringement: For both the ’501 and ’450 patents, the complaint alleges induced and contributory infringement. The allegations state that Defendant provides promotional materials, instructional manuals, and technical materials that encourage and facilitate infringing uses by customers, manufacturers, and distributors. (Compl. ¶16, ¶25). It further alleges the accused FPGA devices are not staple articles of commerce suitable for substantial non-infringing use. (Compl. ¶16, ¶25).
• Willful Infringement: For both patents, the complaint alleges that Defendant has had knowledge of its infringement since at least September 21, 2016, when Plaintiff provided specific notice. (Compl. ¶12, ¶21). The willfulness allegations are based on Defendant's continued infringing activities after receiving this notice. (Compl. ¶17, ¶26).

VII. Analyst’s Conclusion: Key Questions for the Case

This dispute appears to center on highly technical questions of structural conformity at the nanometer scale. The outcome may depend on the answers to the following key questions:

1. A core issue will be one of structural proof: For the ’501 patent, can the plaintiff provide definitive evidence, likely through advanced imaging and analysis, that Xilinx's commercial 28nm FPGAs contain the precise, non-intuitive transistor geometry claimed, specifically the gate electrode "protruding" above a silicon nitride film that does not cover its upper surface?
2. A second key issue will be one of definitional and functional scope: For the ’450 patent, can the term "convex or concave portions" be construed broadly to cover any surface texturing in the accused interconnects, or is its meaning limited by the patent's specification to structures intentionally designed and fabricated for the specific purpose of gettering voids away from a critical contact area?