Tessera Advanced Tech Inc v. Samsung Electronics Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Tessera Advanced Technologies, Inc. (Delaware)
  • Defendant: Samsung Electronics Co., Ltd. (Republic of Korea) and Samsung Electronics America, Inc. (New York)
  • Plaintiff’s Counsel: Latham & Watkins LLP; Ward, Smith & Hill, PLLC
• Case Identification: 2:17-cv-00671, E.D. Tex., 02/20/2018
• Venue Allegations: Venue is alleged to be proper for Samsung Electronics Co., Ltd. as a foreign entity. For Samsung Electronics America, Inc., venue is based on an alleged regular and established place of business within the district, specifically a permanent office in Richardson, Texas, where it employs personnel and conducts business related to the accused cellular mobile devices.
• Core Dispute: Plaintiff alleges that semiconductor components utilizing wafer-level packaging within Defendant’s mobile devices infringe patents related to the structure and manufacturing methods for such components.
• Technical Context: The patents relate to wafer-level chip scale packaging (WLP), a technology that enables the miniaturization and increased performance of semiconductor components essential to modern mobile electronics.
• Key Procedural History: The complaint alleges that Plaintiff disclosed the asserted patents to Defendant and identified allegedly infringing activities on or before May 2, 2016, during discussions concerning technology licensing. This alleged pre-suit notice forms the basis for the willfulness claims.

Case Timeline

Date	Event
2000-11-29	Priority Date for ’298 and ’616 Patents
2003-01-28	U.S. Patent No. 6,512,298 Issues
2005-02-08	U.S. Patent No. 6,852,616 Issues
2016-05-02	Alleged date of pre-suit notice from Plaintiff to Defendant
2018-02-20	First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,512,298 - "Semiconductor Device and Method for Producing the Same," issued January 28, 2003

The Invention Explained

• Problem Addressed: The patent’s background section describes how conventional wafer-level chip scale packages (CSPs) suffer from signal delay caused by electrical resistance in the fine wires that connect the internal electrodes of a semiconductor chip to its external terminals (’298 Patent, col. 2:21-29). This resistance impedes the high-speed signal transmission required by modern electronic equipment.
• The Patented Solution: The invention proposes a hybrid wiring structure for a semiconductor device. To reduce signal delay for high-speed signals, a "first external electrode" is formed immediately above the corresponding internal "element electrode," creating a direct, vertical connection path through an opening in an insulating film. To maintain packaging density, a "second external electrode" is connected to its element electrode via a longer "connecting wire" formed on top of the insulating film, which allows terminals to be repositioned. This structure claims to reduce signal delay for critical connections while preserving the ability to arrange terminals in a two-dimensional array. (’298 Patent, Abstract; col. 2:56-65).
• Technical Importance: This approach sought to resolve a fundamental trade-off between signal speed and packaging density in advanced semiconductor devices. (’298 Patent, col. 2:61-65).

Key Claims at a Glance

• The complaint asserts independent claim 1. (Compl. ¶15).
• The essential elements of independent claim 1 include:
  • a semiconductor substrate provided with at least one semiconductor element;
  • a first element electrode and a second element electrode formed on the semiconductor substrate and connected electrically to the semiconductor element;
  • an insulating film formed so as to cover the first element electrode and the second element electrode;
  • a first opening and a second opening formed on the insulating film, exposing portions of the first and second element electrodes, respectively;
  • a first external electrode formed immediately above the first element electrode and connected to it via the first opening;
  • a second external electrode formed on the insulating film; and
  • a connecting wire formed on the insulating film, connecting the second element electrode (via the second opening) to the second external electrode.
• The complaint reserves the right to assert claims that depend from claim 1. (Compl. ¶15).

U.S. Patent No. 6,852,616 - "Semiconductor Device and Method for Producing the Same," issued February 8, 2005

The Invention Explained

• Problem Addressed: The patent identifies the same problem as its parent '298 patent: signal delay in conventional CSPs due to wiring resistance, which hinders high-speed performance. (’616 Patent, col. 2:25-33).
• The Patented Solution: The ’616 patent claims a specific multi-step method for manufacturing the device structure of the ’298 patent. The process involves forming element electrodes on a substrate, covering them with an insulating film, creating openings in the film, and then using a dual-layer metal deposition process (a first thin conductive film followed by a second thick conductive film) and subsequent patterning to form the final wiring structure, including both the direct vertical connections and the redistributed connecting wires. (’616 Patent, Abstract; col. 5:1-11).
• Technical Importance: The claimed method provides a manufacturing pathway to realize the benefits of the hybrid wiring structure, enabling the mass production of compact, high-speed semiconductor packages. (’616 Patent, col. 5:10-18).

Key Claims at a Glance

• The complaint asserts independent claim 1, a method claim. (Compl. ¶29).
• The essential steps of independent claim 1 include:
  • A first step of forming a first and second element electrode on a semiconductor substrate.
  • A second step of forming an insulating film to cover the electrodes.
  • A third step of forming first and second openings by selectively removing the insulating film.
  • A fourth step of forming a first, substantially continuous, thin conductive film on the insulating film and within the openings.
  • A fifth step of forming a second, thick conductive film selectively on the first thin film to fill the openings and extend over portions of the thin film.
  • A sixth step of patterning both conductive films to form the final structure: a first external electrode, a second external electrode, and a connecting wire.
• The complaint reserves the right to assert claims that depend from claim 1. (Compl. ¶29).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are semiconductor components, specifically identified as wafer-level packaging (WLP) chips such as Power Management IC (“PMIC”) chips, contained within Defendant’s consumer electronic products. (Compl. ¶¶ 15, 29). The complaint names the Samsung Galaxy S6, S7, S8, Note5, Note8, and Tab S3 as devices containing these infringing components. (Compl. ¶15).

Functionality and Market Context

The complaint alleges that the accused components include processors, memory, and other semiconductor parts essential to the function of Samsung's mobile devices. (Compl. ¶13). It specifically highlights the PMIC chips as examples of infringing WLP chips. (Compl. ¶¶ 15, 29). These components are positioned as integral to the operation of high-volume, commercially significant smartphones and tablets.

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

’298 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a semiconductor substrate provided with at least one semiconductor element	The accused WLP chips include a silicon substrate with an integrated circuit containing transistors.	¶16	col. 2:38-39
a first element electrode and a second element electrode formed on the semiconductor substrate and connected electrically to the semiconductor element	The accused WLP chips include a first contact pad and a second contact pad formed on the silicon substrate and connected to transistors.	¶17	col. 2:39-42
an insulating film formed so as to cover the first element electrode and the second element electrode	The accused WLP chips include a polymer insulating layer over the first and second contact pads.	¶18	col. 2:42-44
a first opening formed on the insulating film and exposing at least one portion of the first element electrode	The accused WLP chips have a first opening in the polymer insulating layer that exposes a portion of the first contact pad.	¶19	col. 2:44-46
a second opening formed on the insulating film and exposing at least one portion of the second element electrode	The accused WLP chips have a second opening in the polymer insulating layer that exposes a portion of the second contact pad.	¶20	col. 2:46-48
a first external electrode formed immediately above the first element electrode and connected to the first element electrode via the first opening	The accused WLP chips include a first lower copper-containing layer formed immediately above and connected to the first contact pad via the first opening, on which a first upper copper-containing layer is formed.	¶21	col. 2:48-51
a second external electrode formed on the insulating film	The accused WLP chips include a second lower copper-containing layer formed on the polymer insulating layer, on which a second upper copper-containing layer is formed.	¶22	col. 2:51-52
a connecting wire formed on the insulating film and having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode	The accused WLP chips include a copper-containing wire on the polymer insulating layer, with one end connected to the second contact pad (via the second opening) and the other end connected to the second lower copper-containing layer.	¶23	col. 2:52-55

• Identified Points of Contention:
  • Scope Questions: A primary question will be whether the accused WLP chips embody the specific hybrid structure claimed. The claim recites two distinct connection types: a "first external electrode formed immediately above" its element electrode, and a separate "connecting wire" for the second electrode. The defense may argue that all connections in its WLP chips are made via a functionally indistinct redistribution layer (RDL), and that the complaint’s characterization of "lower copper-containing layers" and "copper-containing wires" artificially separates elements of a single integrated structure.
  • Technical Questions: The infringement allegation hinges on whether the accused structures meet the "immediately above" limitation. A technical question is what evidence the Plaintiff can provide to demonstrate that one set of connections is structurally and functionally different from another in a way that maps onto the claim's distinction between a direct connection and a "connecting wire." The complaint's description is based on "information and belief" and may be challenged with evidence from reverse engineering or discovery.

’616 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a first step of forming on a semiconductor substrate ... a first element electrode and a second element electrode	The process for making the accused WLP chips includes forming a first and second contact pad on a silicon substrate with an integrated circuit.	¶30	col. 4:51-56
a second step of forming an insulating film so as to cover the first element electrode and the second element electrode	The process includes forming a polymer insulating layer above the contact pads.	¶31	col. 4:56-58
a third step of forming a first opening ... and a second opening ... by selectively removing the insulating film	The process includes forming first and second openings in the polymer insulating layer by selectively removing portions of it, exposing the contact pads.	¶32	col. 4:58-64
a fourth step of forming first substantially continuous, thin conductive film on the insulating film and within the first and second openings	The process includes depositing a thin, conductive titanium-containing film on the insulating layer and within the openings.	¶33	col. 11:10-16
a fifth step of forming a second, thick conductive film selectively on the first, thin conductive film so as to fill up the first opening and the second opening and extend over portions of the first, thin conductive film	The process includes selectively forming a thick, copper-containing layer to fill the openings and extend over portions of the thin titanium-containing layer.	¶34	col. 11:26-31
a sixth step of patterning the first and second conductive films by removing only an upper portion of the selectively formed second, thick conductive film and portions of the first, thin conductive film uncovered..., thereby forming a first external electrode..., a second external electrode and forming a connecting wire...	The process includes patterning the copper and titanium films by removing portions to form the final structures, including external electrodes and a connecting wire.	¶35	col. 11:32-50

• Identified Points of Contention:
  • Scope Questions: Infringement is asserted under 35 U.S.C. § 271(g), which requires showing the accused products were made by a process that includes every claimed step. (Compl. ¶29). A central dispute will likely be whether Samsung's proprietary manufacturing process uses the exact sequence of steps claimed, particularly the specific dual-deposition (thin film, then thick film) and subsequent subtractive patterning steps.
  • Technical Questions: The complaint's allegations about the manufacturing process are based on "information and belief." (Compl. ¶30). A key evidentiary question will be whether discovery reveals that Samsung's process actually matches the claim limitations. For example, does Samsung's process truly involve "removing only an upper portion" of the thick conductive film, or does it use a different etching or patterning technique that would fall outside the literal scope of this step?

V. Key Claim Terms for Construction

For the ’298 Patent

• The Term: "immediately above"
• Context and Importance: This term is the lynchpin of the '298 patent's claimed novelty, distinguishing the direct, low-resistance connection from the repositioned "connecting wire." The entire infringement case may turn on whether the accused product's structure has a connection that can be fairly characterized as "immediately above" its corresponding element electrode. Practitioners may focus on this term because it appears to be the primary point of differentiation between the invention and a standard redistribution layer.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent does not explicitly define the term. Plaintiff may argue it requires only vertical alignment between the external and element electrodes, without intervening lateral wiring traces, irrespective of the number of dielectric or passivation layers between them.
  • Evidence for a Narrower Interpretation: Defendant may argue that the term, read in light of the specification, implies a direct and singular vertical connection path. The patent consistently contrasts the electrode "formed immediately above" with the separate "connecting wire," suggesting the terms describe mutually exclusive structures. (’298 Patent, col. 2:56-65). The figures also depict the direct connection (e.g., 11 -> 21 -> 22) as structurally distinct from the wired connection (e.g., 12 -> 21 -> 24 -> 23). (’298 Patent, Fig. 2).

For the ’616 Patent

• The Term: "selectively removing the insulating film"
• Context and Importance: As part of a method claim asserted under § 271(g), the precise meaning of each process step is critical. The interpretation of how the openings are formed will be central to determining if Samsung's manufacturing process infringes.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Plaintiff may argue that this term should be given its plain and ordinary meaning, encompassing any technique that removes the insulating material in designated areas while leaving it in others, such as standard photolithography and etching processes. The specification references using "well-known techniques for exposure and development." (’616 Patent, col. 9:5-9).
  • Evidence for a Narrower Interpretation: Defendant could argue that in the context of the patent's disclosure, the term is tied to the described embodiment of using a "photosensitive insulating material" and a specific development process. (’616 Patent, col. 8:60-65). If Samsung uses a different technology, such as laser ablation or plasma etching of a non-photosensitive material, it may argue its process is not "selectively removing" in the manner taught and claimed by the patent.

VI. Other Allegations

• Indirect Infringement: The complaint alleges Samsung induces infringement of both patents by encouraging others (e.g., customers, distributors) to use and import the accused products. This is allegedly done through "marketing materials, technical specifications, data sheets, web pages... press releases, and user manuals." (Compl. ¶¶ 26, 39).
• Willful Infringement: Willfulness is alleged for both patents. The complaint asserts that Samsung had pre-suit knowledge of the patents and its alleged infringement as of at least May 2, 2016, based on "disclosure" and "discussions regarding... technology licensing" with TATI. (Compl. ¶¶ 24, 37). The complaint alleges Samsung continued its infringing activities despite this knowledge. (Compl. ¶¶ 25, 38).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of structural definition: Can the layered conductive structures within Samsung's accused WLP chips be fairly bifurcated to meet the '298 patent's distinct limitations of a direct "immediately above" connection and a separate "connecting wire," or do they function as a single, undifferentiated redistribution layer that falls outside the claim scope?
• A key evidentiary question will be one of process-product mapping: Under 35 U.S.C. § 271(g), can the plaintiff produce evidence from discovery to demonstrate that Samsung's highly proprietary semiconductor fabrication process practices the specific multi-step sequence of thin and thick film deposition and patterning recited in claim 1 of the '616 patent?
• The viability of the willfulness claim will depend on the nature of pre-suit notice: Did the alleged May 2016 communications provide Samsung with knowledge of infringement so clear and unequivocal that its continued activities could be deemed egregious, or will the facts show they were merely standard, inconclusive licensing negotiations that do not support a finding of willful misconduct?