DCT
2:23-cv-00028
BeSang Inc v. Micron Technology Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: BeSang Inc. (Oregon)
- Defendant: Micron Technology, Inc. (Delaware), Micron Semiconductor Products, Inc. (Idaho), and Micron Technology Texas, LLC (Idaho)
- Plaintiff’s Counsel: Caldwell Cassady & Curry P.C.
- Case Identification: 2:23-cv-00028, E.D. Tex., 01/23/2023
- Venue Allegations: Venue is alleged to be proper based on Defendants committing acts of infringement in the district and maintaining a regular and established place of business in Allen, Texas, which is used for the design of semiconductor memories.
- Core Dispute: Plaintiff alleges that Defendant’s 3D NAND flash memory products, which utilize a "CMOS under Array" architecture, infringe a patent related to vertical semiconductor memory structures.
- Technical Context: The lawsuit concerns 3D NAND flash memory, a technology that vertically stacks memory cells to overcome the physical scaling limitations of traditional 2D memory, enabling higher storage densities in a smaller footprint.
- Key Procedural History: The complaint alleges a long history of interaction between the parties. Plaintiff alleges it made technical presentations to Defendant in 2007 and 2012. It further alleges that the patent-in-suit was cited during the prosecution of over 45 of Defendant's patents, resulting in at least nine rejections. The parties also allegedly engaged in discussions regarding a potential M&A transaction or patent acquisition in 2015, immediately before Defendant announced its first 3D NAND products.
Case Timeline
| Date | Event |
|---|---|
| 2004-06-21 | '702 Patent Priority Date |
| 2007-07-01 | BeSang presents its 3D technology to Micron (approximate date) |
| 2008-05-27 | '702 Patent Issue Date |
| 2012-05-01 | BeSang inventor presents at IEEE workshop attended by Micron staff |
| 2015-03-23 | Micron and BeSang discuss potential M&A transaction |
| 2015-03-26 | Micron announces its first 3D NAND flash memory technology |
| 2015-03-27 | Micron discusses acquiring BeSang's patents |
| 2016-01-01 | Micron incorporates 3D NAND tech into products (at least as early as) |
| 2022-07-01 | Micron announces 232-Layer NAND memory (approximate date) |
| 2023-01-23 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,378,702 - “Vertical Memory Device Structures”
- Patent Identification: U.S. Patent No. 7,378,702, titled “Vertical Memory Device Structures,” issued on May 27, 2008.
The Invention Explained
- Problem Addressed: The patent addresses the need for methods to provide "increased circuit density in integrated circuits without necessarily requiring devices to be made smaller" (’702 Patent, col. 2:40-44). The complaint frames this problem as conventional 2D NAND memory "nearing its practical scaling limits, posing significant challenges for the memory industry" (Compl. ¶23).
- The Patented Solution: The invention proposes a three-dimensional architecture where vertically oriented memory cells are fabricated in a "stackable add-on layer" that is subsequently bonded to a separately fabricated substrate containing other electrical components, such as logic circuits (’702 Patent, Abstract; col. 4:53-58). This structure, illustrated in Figure 1 of the patent, places the memory array (101) above the logic circuitry (114), allowing for expansion into the third dimension and thereby increasing density and performance (Compl. ¶25; ’702 Patent, Fig. 1).
- Technical Importance: This approach provided a pathway to continue increasing memory capacity by building vertically, a fundamental shift from the traditional method of shrinking components laterally on a two-dimensional plane (Compl. ¶25).
Key Claims at a Glance
- The complaint asserts independent claim 13 (Compl. ¶52).
- The essential elements of independent claim 13 are:
- A substrate having electrical devices formed therein;
- A dielectric layer disposed above the electrical devices;
- A stackable add-on layer having a plurality of vertically oriented semiconductor memory cells;
- The stackable add-on layer being bonded to the dielectric layer; and
- The memory cells are nonvolatile and have at least one transistor.
- The complaint notes that the selection of claims is not limiting and that additional claims may be asserted later (Compl. ¶46).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are Micron’s 3D NAND flash memory products, including chips and devices incorporating them like SSDs, eMMC, and UFS devices (Compl. ¶6). The complaint specifically lists products with 32, 64, 96, 176, and 232 layers of memory cells and identifies the Micron 3400 SSD and Micron B16A UFS as representative products (Compl. ¶¶41, 63, 81).
Functionality and Market Context
- The complaint alleges that all accused products utilize a "CMOS under Array" ("CuA") architecture, which places peripheral logic circuitry underneath the vertical memory array (Compl. ¶56). This architecture is described as a "critical breakthrough" for Micron, enabling smaller die sizes and improved performance (Compl. ¶¶39, 45). The complaint includes marketing material, such as a diagram for Micron's 64-layer product, that explicitly features "CMOS under Array (CuA) for most efficient die size" (Compl. p. 13).
IV. Analysis of Infringement Allegations
'702 Patent Infringement Allegations
| Claim Element (from Independent Claim 13) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| [13a] a substrate having electrical devices formed therein | The accused products contain a substrate with CMOS control circuits formed within it. | ¶¶66-67 | col. 5:59-63 |
| [13b] further having a dielectric layer disposed above the electrical devices | The accused products contain a dielectric layer positioned over the CMOS circuits. | ¶¶68-69 | col. 12:4-6 |
| [13c] a stackable add-on layer having a plurality of vertically oriented semiconductor memory cells | The accused products feature a memory array composed of multiple layers of vertically oriented NAND memory cells. | ¶¶71-73 | col. 12:7-10 |
| [13d] the stackable add-on layer being bonded to the dielectric layer | The memory array layer is bonded to the underlying dielectric layer. | ¶¶75-76 | col. 12:11-12 |
| [13e] wherein the memory cells are nonvolatile memory cells having at least one transistor | The accused products' memory cells are NAND cells, which are a form of nonvolatile memory and are comprised of transistors. | ¶¶77-79 | col. 12:15-17 |
- Identified Points of Contention:
- Scope Questions: The complaint uses annotated cross-section images to illustrate the alleged infringement, such as one identifying the CMOS circuits in the substrate (Compl. p. 18). A primary point of dispute may concern the claim term "bonded to." The patent describes a process of bonding a separately fabricated "stackable add-on layer" (e.g., an SOI wafer) to a substrate. The infringement analysis will raise the question of whether Micron's integrated "CMOS under Array" manufacturing process, which may build the layers monolithically, falls within the patent's definition of "bonding" two distinct components.
- Technical Questions: The complaint alleges that a cross-section of a Micron 3D NAND chip shows a distinct memory array (annotated in blue) bonded to a dielectric layer (Compl. p. 20, 22). A technical question for the court will be whether the physical structure of the accused products exhibits the discrete "substrate," "dielectric layer," and "stackable add-on layer" required by the claim, or if the boundaries between these elements in Micron's integrated CuA process are indistinct in a way that avoids infringement.
V. Key Claim Terms for Construction
The Term: "stackable add-on layer"
- Context and Importance: This term defines the core inventive concept of adding a prefabricated memory layer. Practitioners may focus on this term because its construction will determine whether the claim is limited to a specific layer-transfer manufacturing method or broadly covers any structure with memory built on top of logic.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The Summary of the Invention states that memory devices "are added to a separately fabricated substrate" (’702 Patent, col. 2:50-52), which could be interpreted as covering any process that results in this final structure.
- Evidence for a Narrower Interpretation: The Detailed Description suggests a more specific process, defining the layer as a "single crystal portion of a semiconductor wafer that can be cleaved and bonded to another previously fabricated wafer" (’702 Patent, col. 4:49-52), which may support a narrower construction limited to wafer-bonding techniques.
The Term: "bonded to"
- Context and Importance: This term is critical as it defines the required relationship between the memory layer and the underlying dielectric layer. Its meaning is directly tied to the interpretation of "stackable add-on layer."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The term itself is not explicitly defined, which may support an argument that it should be given its plain and ordinary meaning of being joined or fastened, which could encompass various semiconductor manufacturing techniques.
- Evidence for a Narrower Interpretation: The context of the specification, which repeatedly discusses combining a "transferred, unpatterned, SOI layer" with a substrate, may support a narrower definition limited to the act of joining two previously separate and distinct layers (’702 Patent, col. 5:20-25).
VI. Other Allegations
- Indirect Infringement: The complaint alleges that Micron induces infringement by providing "specifications, datasheets, instruction manuals, support materials...and user guide materials" that instruct customers and end-users on how to use the accused 3D NAND products in an infringing manner (Compl. ¶100).
- Willful Infringement: The complaint alleges willful infringement based on Micron’s purported pre-suit knowledge of the ’702 Patent. The alleged bases for this knowledge include a 2007 presentation by Plaintiff to Defendant, the patent’s citation during the prosecution of Defendant’s own patent applications, Defendant's employees attending a 2012 technical presentation by the inventor, and M&A/licensing discussions in 2015 (Compl. ¶¶31-37, 107).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue will be one of claim scope and construction: does Claim 13 of the '702 patent, which describes a "stackable add-on layer" that is "bonded to" a substrate, cover any resulting 3D memory structure with logic underneath, or is its scope limited to structures created by the specific layer-transfer-and-bonding manufacturing process detailed in the patent's specification? The answer will likely depend on the court's interpretation of these key terms.
- A key evidentiary question will be one of structural and procedural equivalence: does Micron’s proprietary "CMOS under Array" (CuA) manufacturing process create a final product with discrete, identifiable layers that meet the structural limitations of Claim 13? Or does Micron’s potentially monolithic fabrication method differ sufficiently from the patent's described layer-bonding process to fall outside the scope of the claims?