DCT

2:24-cv-00623

Advanced Integrated Circuit Process LLC v. Taiwan Semiconductor Mfg Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:24-cv-00623, E.D. Tex., 08/01/2024
  • Venue Allegations: The complaint alleges venue is proper because the Defendant is not a resident of the United States and may therefore be sued in any judicial district.
  • Core Dispute: Plaintiff alleges that Defendant’s semiconductor devices, manufactured using its advanced process nodes, infringe seven patents related to the structure and fabrication of transistors.
  • Technical Context: The technology at issue involves fundamental transistor structures (MISFETs and FinFETs) used in advanced semiconductor manufacturing, which is critical to the performance of modern electronics from smartphones to high-performance computing.
  • Key Procedural History: The complaint alleges that Defendant had knowledge of the asserted patent families since at least 2012, based on citations made by the U.S. Patent and Trademark Office against Defendant's own patent applications during their prosecution. This history may be central to the allegations of willful infringement.

Case Timeline

Date Event
2005-08-05 Priority Date for ’227, ’764, ’180, and ’076 Patents
2008-03-13 Priority Date for ’686 Patent
2009-08-25 ’227 Patent Issued
2010-01-07 Priority Date for ’425 Patent
2010-09-14 Priority Date for ’779 Patent
2011-04-12 ’764 Patent Issued
2012-01-01 Alleged knowledge of asserted patent family by TSMC begins "at least 2012"
2012-06-12 ’686 Patent Issued
2012-08-28 ’180 Patent Issued
2013-11-19 ’076 Patent Issued
2014-07-01 Samples of Accused T2081 Product available (2H-2014)
2014-08-05 ’779 Patent Issued
2014-12-09 ’425 Patent Issued
2021-09-24 Approximate launch of Accused A15 Bionic Product with iPhone 13
2024-08-01 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,579,227 - “Semiconductor Device and Method for Fabricating the Same”

Issued August 25, 2009.

The Invention Explained

  • Problem Addressed: In conventional metal-insulator-semiconductor field-effect transistors (MISFETs) that use a high dielectric constant (high-k) material for the gate insulating film, the side edges of that film are in direct contact with the insulating sidewalls formed alongside the gate. This contact can alter the composition of the high-k film, degrading its dielectric properties and reducing the transistor's performance and reliability (’227 Patent, col. 1:53-65).
  • The Patented Solution: The invention proposes a transistor structure where the high-k gate insulating film is continuous, extending from underneath the gate electrode to underneath the insulating sidewall. Critically, the portion of the high-k film located under the sidewall is fabricated to be thinner than the portion directly under the gate electrode (’227 Patent, col. 2:32-49; Abstract). This structure maintains the integrity of the high-k film at the gate edge while the thinner portion helps reduce unwanted parasitic capacitance, which could otherwise slow down circuit speed (’227 Patent, col. 4:45-54).
  • Technical Importance: The invention provides a structural approach to mitigate reliability issues and performance trade-offs inherent in scaling transistors with high-k gate materials.

Key Claims at a Glance

  • The complaint asserts at least independent Claim 1 (Compl. ¶72).
  • The essential elements of Claim 1 include:
    • A semiconductor device comprising a high dielectric constant gate insulating film, a gate electrode on top of it, and an insulating sidewall on the side of the gate electrode.
    • The high dielectric constant gate insulating film is continuously formed to extend from under the gate electrode to under the insulating sidewall.
    • At least part of the high-k film under the insulating sidewall has a smaller thickness than the part under the gate electrode.
    • The insulating sidewall includes a first insulating sidewall and a second insulating sidewall.
  • The complaint does not explicitly reserve the right to assert dependent claims for the ’227 Patent.

U.S. Patent No. 7,923,764 - “Semiconductor Device and Method for Fabricating the Same”

Issued April 12, 2011.

The Invention Explained

  • Problem Addressed: This patent, a divisional of the application that led to the ’227 Patent, addresses the same technical problem of degradation of the high-k gate insulating film at the gate edge due to contact with sidewall materials (’764 Patent, col. 1:60-col. 2:2).
  • The Patented Solution: The ’764 Patent claims a similar solution: a transistor structure where the high-k gate insulating film extends continuously from under the gate electrode to under a first insulating sidewall. As in the parent patent, the portion of the high-k film under this sidewall is thinner than the portion under the gate electrode, which is intended to suppress parasitic capacitance while maintaining the film's integrity (’764 Patent, col. 2:40-54; Abstract).
  • Technical Importance: This patent claims a variation of the structural solution for improving performance and reliability in advanced MISFETs using high-k gate dielectrics.

Key Claims at a Glance

  • The complaint asserts at least independent Claim 1 (Compl. ¶92).

  • The essential elements of Claim 1 include:

    • A semiconductor device with a high dielectric constant gate insulating film, a gate electrode, a first insulating sidewall, and a second insulating sidewall.
    • The high dielectric constant gate insulating film is continuously formed to extend from under the gate electrode to under the first insulating sidewall.
    • Part of the high-k film under the first insulating sidewall has a smaller thickness than the part located under the gate electrode.

  • The complaint does not explicitly reserve the right to assert dependent claims for the ’764 Patent.

  • Multi-Patent Capsule: U.S. Patent No. 8,198,686, “Semiconductor Device,” issued June 12, 2012.

    • Technology Synopsis: The patent describes a semiconductor device containing two different types of MIS transistors (e.g., NMOS and PMOS). The gate structures are differentiated by using different metal films, and a silicon nitride film is used to introduce stress into the channel of one transistor to enhance its performance (Compl. ¶108, ¶110, ¶113-114).
    • Asserted Claims: At least independent Claim 25 (Compl. ¶107).
    • Accused Features: The complaint accuses the T2081 device and other products from TSMC’s 28nm process node, which allegedly include NMOS and PMOS transistors with the claimed differential gate materials and stress-inducing films (Compl. ¶110-114).

  • Multi-Patent Capsule: U.S. Patent No. 8,253,180, “Semiconductor Device,” issued August 28, 2012.

    • Technology Synopsis: This patent, from the same family as the ’227 and ’764 patents, claims a semiconductor device with a high-k gate insulating film that extends continuously under the gate and an adjacent sidewall. It specifically claims that the end of the high-k film under the sidewall is located at a "predetermined distance" from the outer edge of that sidewall, defining the extent of the film's termination (Compl. ¶125).
    • Asserted Claims: At least independent Claim 1 (Compl. ¶124).
    • Accused Features: The complaint accuses the T2081 device and other products from TSMC’s 28nm process node of having this specific gate insulating film structure (Compl. ¶127-128).

  • Multi-Patent Capsule: U.S. Patent No. 8,587,076, “Semiconductor Device,” issued November 19, 2013.

    • Technology Synopsis: This patent, also from the ’227 patent family, describes a device with a gate insulating film containing hafnium (Hf). The claims require that the width of this insulating film be larger than the width of the gate electrode itself, and that the end of the film under the sidewall be "retracted" toward the gate electrode (Compl. ¶139).
    • Asserted Claims: At least independent Claim 1 (Compl. ¶138).
    • Accused Features: The complaint accuses the T2081 device and other products from TSMC’s 28nm process node (Compl. ¶141-142).

  • Multi-Patent Capsule: U.S. Patent No. 8,796,779, “Semiconductor Device,” issued August 5, 2014.

    • Technology Synopsis: This patent describes a device with two MIS transistors of the same conductivity type (e.g., both PMOS) on the same substrate. The invention is that the first transistor has a gate insulating film with a thicker "interface layer" (e.g., silicon dioxide) than the second transistor, allowing for transistors with different performance characteristics on the same chip (Compl. ¶154, ¶162).
    • Asserted Claims: At least independent Claim 1 (Compl. ¶153).
    • Accused Features: The complaint accuses the Apple A15 Bionic and other FinFET devices from TSMC's 5, 7, 10, 14, 16, and 20 nm process nodes (Compl. ¶70, ¶156, ¶163). A photograph of the Apple A15 Bionic chip is provided as visual evidence (Compl. p. 16).

  • Multi-Patent Capsule: U.S. Patent No. 8,907,425, “Semiconductor Device,” issued December 9, 2014.

    • Technology Synopsis: This patent claims a transistor structure designed to enhance performance through mechanical stress. It includes a "stress insulating film" covering the transistor and a "stress-relief film" positioned between the source/drain region (which includes a silicon compound like SiGe) and the sidewall spacer, aiming to manage the stresses applied to the transistor channel (Compl. ¶175).
    • Asserted Claims: At least independent Claim 1 (Compl. ¶174).
    • Accused Features: The complaint accuses MediaTek devices and other products from TSMC's 28nm process node (Compl. ¶66, ¶174, ¶177).

III. The Accused Instrumentality

Product Identification

The complaint identifies two broad categories of accused products based on TSMC's manufacturing processes (Compl. ¶67, ¶70):

  1. "Accused 28nm Instrumentalities": Semiconductor devices manufactured using TSMC's 28 nanometer process node. Exemplars include the NXP T2081 device and devices made for MediaTek.
  2. "Accused FinFET Instrumentalities": Semiconductor devices manufactured using TSMC's 5, 7, 10, and 16 nanometer FinFET process nodes. The exemplar is the Apple A15 Bionic semiconductor device.

Functionality and Market Context

The accused instrumentalities are foundational semiconductor components manufactured by TSMC, a leading global foundry, for major technology companies like NXP, MediaTek, and Apple (Compl. ¶63, ¶66, ¶68). These devices are incorporated into a wide array of end-user electronics (Compl. ¶62). The complaint provides visual evidence identifying the accused NXP T2081 device as being manufactured using the "TSMC 28HPM Process" (Compl. p. 12, p. 14). A table from an NXP document further identifies the "Process Technology" for the T2081 as "TSMC 28HPM" (Compl. p. 15).

IV. Analysis of Infringement Allegations

’227 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a high dielectric constant gate insulating film formed on an active region in a substrate; The T2081 device comprises a high dielectric constant gate insulating film formed on an active region in a substrate. ¶75 col. 2:40-42
a gate electrode formed on the high dielectric constant gate insulating film; The T2081 device comprises a gate electrode formed on the high dielectric constant gate insulating film. ¶75 col. 2:40-42
an insulating sidewall formed on each side surface of the gate electrode, The T2081 device comprises an insulating sidewall formed on each side surface of the gate electrode. ¶75 col. 2:42-44
wherein the high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall, The high dielectric constant gate insulating film in the T2081 device is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. ¶75 col. 2:44-46
at least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode, The complaint alleges that in the T2081 device, the "tapered edge" of the high dielectric constant insulating film is thinner than the non-tapered area under the gate electrode. ¶76 col. 2:46-49
the insulating sidewall includes a first insulating sidewall formed on a side surface of the gate electrode and a second insulating sidewall formed on the side surface of the gate electrode with the first insulating sidewall interposed therebetween, The T2081 device's insulating sidewall allegedly includes a first insulating sidewall and a second insulating sidewall arranged as claimed. ¶77 col. 2:50-55

’764 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a high dielectric constant gate insulating film formed on an active region in a substrate; The T2081 is a semiconductor device comprising a high dielectric constant gate insulating film formed on an active region in a substrate. ¶95 col. 2:44-46
a gate electrode formed on the high dielectric constant gate insulating film; The T2081 comprises a gate electrode formed on the high dielectric constant gate insulating film. ¶95 col. 2:44-46
a first insulating sidewall formed on each side surface of the gate electrode; and a second insulating sidewall formed on said each side surface of the gate electrode with the first insulating sidewall interposed therebetween, The T2081 comprises a first insulating sidewall and a second insulating sidewall arranged as claimed on the side surfaces of the gate electrode. ¶95 col. 2:47-51
wherein the high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the first insulating sidewall, The high dielectric constant gate insulating film in the T2081 device is alleged to be continuously formed to extend from under the gate electrode to under the first insulating sidewall. ¶95 col. 3:1-4
and part of the high dielectric constant gate insulating film located under the first insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode. The complaint alleges that in the T2081, the "tapered edge" of the high dielectric constant insulating film is thinner than the non-tapered area under the gate electrode. ¶96 col. 3:4-8
  • Identified Points of Contention:
    • Technical Questions: The infringement allegations for both the ’227 and ’764 patents rely on the assertion that a "tapered edge" of the high-k film in the accused devices satisfies the "smaller thickness" limitation (Compl. ¶76, ¶96). A primary technical question will be what evidence exists to demonstrate that this tapering is a deliberate, functional feature corresponding to the patented structure, rather than an incidental artifact of the manufacturing process. The complaint does not provide detailed structural analysis, such as microscopy images, to support this allegation.
    • Scope Questions: The case may raise the question of whether the term "continuously formed," as described in the patents, requires a specific manufacturing sequence. The defendant may argue that its process, even if resulting in a superficially similar structure, does not meet the claim limitations when read in light of the specification's teachings on fabrication.

V. Key Claim Terms for Construction

  • The Term: "a smaller thickness" (appearing in Claim 1 of both the ’227 and ’764 patents)
  • Context and Importance: This term is central to the dispute, as the plaintiff's infringement theory rests on the allegation that a "tapered edge" in the accused T2081 device meets this limitation (Compl. ¶76, ¶96). Practitioners may focus on this term because its construction will determine whether incidental process variations are sufficient to prove infringement, or if a more specific, controlled structural profile is required.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The plain language of the claim simply requires that one part of the film has "a smaller thickness" than another part, without specifying a particular shape, ratio, or method of formation (’227 Patent, col. 22:1-3).
    • Evidence for a Narrower Interpretation: The patent specification describes forming this thinner portion as a distinct process step to achieve a specific technical benefit—reducing parasitic capacitance while avoiding reliability issues (’227 Patent, col. 4:45-54). The patent figures (e.g., ’227 Patent, Fig. 1) depict a distinct convex shape rather than a gradual taper, which may support an argument that the claim requires a specific, engineered profile, not just any variance in thickness at the film's edge.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that TSMC induced infringement by actively encouraging its customers, such as NXP Semiconductors, to use its allegedly infringing 28nm and FinFET process nodes (Compl. ¶80, ¶98, ¶164). The allegations state TSMC touted the "technological and economic benefits" of these nodes through its sales and marketing staff and provided technical assistance, thereby encouraging the use, sale, and importation of products containing the accused devices (Compl. ¶80, ¶98).
  • Willful Infringement: The complaint alleges willful infringement based on pre-suit knowledge of the asserted patent families. It claims TSMC has known of the patents since "at least 2012" because the U.S. Patent and Trademark Office cited applications from the asserted patent family as references during the prosecution of TSMC's own U.S. Patent No. 8,258,588 and other TSMC patents (Compl. ¶88, ¶103, ¶135, ¶149).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A key evidentiary question will be one of structural proof: what technical evidence, such as cross-sectional analysis, can the plaintiff provide to demonstrate that the accused semiconductor devices possess the specific gate structures claimed in the patents—particularly the controlled, "smaller thickness" of the high-k dielectric film under the sidewall—beyond the general allegation of a "tapered edge"?
  • A central issue for claim construction will be one of definitional scope: can the claim limitation "a smaller thickness" be construed broadly to encompass any incidental tapering resulting from a manufacturing process, or does the intrinsic evidence limit the term to a specific, engineered profile intended to achieve the technical benefits described in the patent?
  • For damages and willfulness, a core question will be one of effective knowledge: did the patent prosecution citations from 2012 and later provide TSMC with actual knowledge of the specific patented inventions sufficient to establish that its continued manufacturing activities constituted deliberate and willful infringement?