Advanced Integrated Circuit Process LLC v. United Microelectronics Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Advanced Integrated Circuit Process LLC (Texas)
  • Defendant: United Microelectronics Corporation (Taiwan)
  • Plaintiff’s Counsel: Susman Godfrey LLP
• Case Identification: 2:24-cv-00730, E.D. Tex., 09/06/2024
• Venue Allegations: Plaintiff alleges that because Defendant is not a resident of the United States, venue is proper in any judicial district pursuant to 28 U.S.C. §§ 1391(c)(3) and 1400(b).
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor devices, manufactured using its 22-nanometer and 28-nanometer process nodes, infringe seven patents related to the structure and fabrication of Metal-Insulator-Semiconductor Field-Effect Transistors (MISFETs).
• Technical Context: The technology relates to the physical structure of transistors, the fundamental building blocks of modern electronics, focusing on techniques to improve performance and reliability as device features shrink to the nanometer scale.
• Key Procedural History: The complaint alleges that Defendant has had actual knowledge of the ’425 Patent since at least 2019, when the patent was cited by the U.S. Patent and Trademark Office during the prosecution of one of Defendant's own patents, which forms the basis for a willfulness allegation.

Case Timeline

Date	Event
2005-08-05	Priority Date for ’227, ’764, ’180, and ’076 Patents
2008-03-13	Priority Date for ’686 Patent
2009-08-25	’227 Patent Issued
2010-01-07	Priority Date for ’425 Patent
2010-09-14	Priority Date for ’779 Patent
2011-04-12	’764 Patent Issued
2012-06-12	’686 Patent Issued
2012-08-28	’180 Patent Issued
2013-11-19	’076 Patent Issued
2014-08-05	’779 Patent Issued
2014-12-09	’425 Patent Issued
2019-01-01	Alleged Knowledge Date for ’425 Patent Willfulness
2024-09-06	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,579,227 - Semiconductor Device and Method for Fabricating the Same (Issued August 25, 2009)

The Invention Explained

• Problem Addressed: The patent addresses a problem in advanced transistors (MISFETs) that use high-dielectric-constant (high-k) materials for the gate insulating film. When the side edges of this high-k film come into direct contact with other materials like silicon oxide during fabrication, its chemical composition can change, degrading its insulating properties and reducing the transistor's reliability and performance (Compl. ¶37; ’227 Patent, col. 1:56-col. 2:3).
• The Patented Solution: The invention proposes a specific transistor structure to shield the edges of the high-k film. The high-k film is formed as a continuous layer that extends from directly underneath the gate electrode to underneath the insulating sidewalls adjacent to the gate. A key aspect of the solution is that the portion of the high-k film located under the sidewall is intentionally made thinner than the portion directly under the gate electrode. This design prevents the vulnerable edge of the film from contacting other materials while the thinner profile helps reduce unwanted electrical capacitance that could slow the circuit down (’227 Patent, Abstract; col. 2:32-49).
• Technical Importance: This approach sought to resolve a critical manufacturing and reliability challenge associated with the industry's transition to high-k materials, a necessary step for continuing to shrink transistors and improve the performance of integrated circuits (’227 Patent, col. 1:16-24).

Key Claims at a Glance

• The complaint asserts independent Claim 1 (Compl. ¶73).
• The essential elements of Claim 1 include:
  • A semiconductor device comprising a high dielectric constant gate insulating film, a gate electrode on the film, and an insulating sidewall on the side of the gate electrode.
  • The high dielectric constant gate insulating film is continuously formed to extend from under the gate electrode to under the insulating sidewall.
  • A portion of the gate insulating film under the sidewall has a smaller thickness than the portion under the gate electrode.
  • The insulating sidewall itself comprises a "first" and a "second" insulating sidewall, with the first being closer to the gate electrode.
  • The continuous gate insulating film extends under the first insulating sidewall, and the portion of the film under that first sidewall has a smaller thickness than the portion under the gate electrode.
• The complaint alleges infringement of "at least Claim 1," suggesting the right to assert dependent claims is preserved (Compl. ¶72).

U.S. Patent No. 7,923,764 - Semiconductor Device and Method for Fabricating the Same (Issued April 12, 2011)

The Invention Explained

• Problem Addressed: As a divisional of the application leading to the ’227 Patent, this patent addresses the same technical problem: the degradation of high-k gate insulating films at their edges due to contact with other materials during fabrication, which harms device performance and reliability (Compl. ¶42; ’764 Patent, col. 1:60-col. 2:3).
• The Patented Solution: The solution is structurally similar to that of the ’227 Patent. It claims a transistor where the high-k film is continuous from under the gate electrode to under an adjacent "first insulating sidewall." The portion of the high-k film under this first sidewall is thinner than the portion directly under the gate electrode, thereby protecting the film's integrity while managing parasitic capacitance (’764 Patent, Abstract; col. 2:56-68).
• Technical Importance: The invention provided a structural solution to enable the use of high-k dielectrics, which was essential for continued transistor scaling and performance improvements in the semiconductor industry (’764 Patent, col. 1:17-25).

Key Claims at a Glance

• The complaint asserts independent Claim 1 (Compl. ¶91).
• The essential elements of Claim 1 include:
  • A semiconductor device comprising a high dielectric constant gate insulating film, a gate electrode, a first insulating sidewall, and a second insulating sidewall.
  • The high dielectric constant gate insulating film is continuously formed to extend from under the gate electrode to under the first insulating sidewall.
  • A portion of the high dielectric constant gate insulating film located under the first insulating sidewall has a smaller thickness than the portion of the film located under the gate electrode.
• The complaint alleges infringement of "at least Claim 1," suggesting the right to assert dependent claims is preserved (Compl. ¶90).

U.S. Patent No. 8,198,686 - Semiconductor Device (Issued June 12, 2012)

• Technology Synopsis: This patent claims a semiconductor device containing two distinct MIS transistors (e.g., an NMOS and a PMOS transistor). The invention specifies different metal films for the gate electrodes of each transistor type and a silicon nitride stress-inducing film that extends over the device but is explicitly not formed on the upper surfaces of the gate electrodes (Compl. ¶¶56, 104).
• Asserted Claims: Claim 25 (Compl. ¶104).
• Accused Features: The complaint accuses the NMOS and PMOS transistors in the MDM9625M device, alleging they use different metal films (TiN and TaN) and a silicon nitride film that induces stress, consistent with the claim (Compl. ¶¶106-110).

U.S. Patent No. 8,253,180 - Semiconductor Device (Issued August 28, 2012)

• Technology Synopsis: This patent, from the same family as the ’227 and ’764 Patents, claims a structure where a continuous high-k gate insulating film extends under an insulating sidewall. The claim focuses on the specific location of the film's termination point, requiring that an "end" of the film under the sidewall be "located at a predetermined distance from an outer end of the insulating sidewall" (Compl. ¶¶47, 120).
• Asserted Claims: Claim 1 (Compl. ¶120).
• Accused Features: The alleged structure of the high-k gate insulating film in the MDM9625M device is accused of meeting the claimed termination-point limitation (Compl. ¶¶122-123).

U.S. Patent No. 8,587,076 - Semiconductor Device (Issued November 19, 2013)

• Technology Synopsis: Also from the same family as the ’227 Patent, this patent claims a device where the gate insulating film includes Hafnium (Hf). The claims require the width of this Hf-including film to be larger than the width of the gate electrode and for the end of the film under the sidewall to be "retracted" from the sidewall's outer edge (Compl. ¶¶52, 133).
• Asserted Claims: Claim 1 (Compl. ¶133).
• Accused Features: The MDM9625M's gate insulating film, alleged to contain Hafnium and have a specific geometry relative to the gate electrode and sidewall, is the accused feature (Compl. ¶¶135-136).

U.S. Patent No. 8,796,779 - Semiconductor Device (Issued August 5, 2014)

• Technology Synopsis: This patent claims a device with two MIS transistors of the identical conductivity type on the same substrate. The invention requires that the gate insulating films of these two transistors have different structures, specifically that the "first interface layer" (e.g., silicon dioxide) of one is thicker than the "second interface layer" of the other (Compl. ¶¶60, 146).
• Asserted Claims: Claim 1 (Compl. ¶146).
• Accused Features: The complaint accuses the MDM9625M device of containing two PMOS transistors with interface layers of different thicknesses to meet the claim limitations (Compl. ¶¶148, 154).

U.S. Patent No. 8,907,425 - Semiconductor Device (Issued December 9, 2014)

• Technology Synopsis: This patent claims a transistor structure designed to manage mechanical stress to enhance performance. It requires a silicon compound layer (e.g., SiGe) in the source/drain region to cause a "first stress," an opposing "second stress" from a stress insulating film, and a "first stress-relief film" located in a space between the silicon compound layer and the sidewall spacer (Compl. ¶¶64, 164).
• Asserted Claims: Claim 1 (Compl. ¶164).
• Accused Features: The complaint identifies the Microsemi PolarFire device as an exemplar. A photograph shows the accused PolarFire chip (Compl. p. 14). The complaint alleges the PolarFire device contains the claimed silicon compound layer, stress insulating film, and stress-relief film (Compl. ¶¶166-170).

III. The Accused Instrumentality

Product Identification

The "Accused Instrumentalities" are defined as all semiconductor devices manufactured by Defendant UMC using its 22-nanometer and 28-nanometer process nodes (Compl. ¶70). The complaint identifies two specific exemplars: the Qualcomm MDM9625M modem chipset and the Microsemi (a Microchip subsidiary) PolarFire FPGA devices (Compl. ¶¶68-69). A photograph of the accused Qualcomm MDM9625M chip is provided in the complaint (Compl. p. 13).

Functionality and Market Context

The accused devices are advanced integrated circuits that form the core components of modern electronic products. The complaint alleges that these devices are manufactured for major UMC customers such as Qualcomm and are incorporated into high-volume consumer products, including Apple's iPhones and iPads (Compl. ¶16). The complaint further alleges that the 22nm and 28nm process nodes are a key part of UMC's business, described as a "sweet spot" that drives a significant portion of its revenue (Compl. ¶¶83-84).

IV. Analysis of Infringement Allegations

’227 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode,	The MDM9625M device is a semiconductor device comprising these fundamental transistor components.	¶75	col. 2:38-43
wherein the high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall,	The MDM9625M is alleged to have a high dielectric constant gate insulating film that is continuously formed to extend from under the gate electrode to under the insulating sidewall.	¶75	col. 2:43-46
at least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode,	The complaint alleges that in the MDM9625M, the "tapered edge" of the high dielectric constant insulating film is thinner than the non-tapered area under the gate electrode.	¶76	col. 2:46-49
the insulating sidewall includes a first insulating sidewall formed on a side surface of the gate electrode and a second insulating sidewall formed on the side surface of the gate electrode with the first insulating sidewall interposed therebetween,	The MDM9625M is alleged to have an insulating sidewall that includes a first and second insulating sidewall.	¶77	col. 2:50-55
the high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the first insulating sidewall, and	The MDM9625M is alleged to have a high dielectric constant gate insulating film that continuously extends under the first insulating sidewall.	¶77	col. 2:55-58
part of the high dielectric constant gate insulating film located under the first insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.	The complaint alleges this structural feature is present in the MDM9625M device.	¶78	col. 2:58-62

Identified Points of Contention

• Technical Questions: The complaint's infringement theory rests on narrative descriptions of the accused device's structure (e.g., a "tapered edge"). A central question will be what technical evidence exists to show that the physical, nanometer-scale structure of the MDM9625M chip meets the specific geometric requirements of Claim 1, such as the presence of distinct "first" and "second" insulating sidewalls and a quantifiable "smaller thickness" of the film underneath the first sidewall.
• Scope Questions: Claim 1 recites a complex, multi-part sidewall structure. The analysis may raise the question of whether the structures created by UMC's 28nm manufacturing process, as a matter of course, fall within the scope of these specific claim limitations, or if there is a technical distinction between the claimed structure and the accused product.

’764 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; a first insulating sidewall formed on each side surface of the gate electrode; and a second insulating sidewall formed on said each side surface...	The MDM9625M device is alleged to comprise these components, including a first and second insulating sidewall.	¶93	col. 2:58-63
wherein the high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the first insulating sidewall, and	The MDM9625M is alleged to have a high dielectric constant gate insulating film that continuously extends under the first insulating sidewall.	¶93	col. 2:63-66
part of the high dielectric constant gate insulating film located under the first insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.	The complaint alleges that in the MDM9625M, the "tapered edge" of the high dielectric constant insulating film meets this "smaller thickness" requirement.	¶94	col. 2:66-68

Identified Points of Contention

• Technical Questions: Similar to the ’227 Patent, a key question will be evidentiary: what proof demonstrates that the accused device's actual physical structure contains a "first" and "second" sidewall and that the film thickness under the first is measurably "smaller" than the film thickness under the gate electrode? The complaint's reliance on a "tapered edge" allegation will require technical validation against the claim language.
• Scope Questions: The term "smaller thickness" may be a point of contention. The analysis may question whether any tapering of the film edge resulting from a standard manufacturing process meets this limitation, or if the patent's specification requires a more distinct, intentionally created step-down in thickness.

V. Key Claim Terms for Construction

"smaller thickness" (asserted in Claim 1 of both the ’227 and ’764 Patents)

• Context and Importance: This term is central to the inventive concept of both patents, defining the structural relationship that allegedly solves the technical problem of edge degradation while managing capacitance. The dispute may turn on whether the alleged "tapered edge" of the accused device's film (Compl. ¶¶76, 94) satisfies this limitation. Practitioners may focus on this term because its construction will determine whether a natural process artifact (tapering) infringes a claim that may be read to require a more deliberate structural change.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes a fabrication step of "etching...to reduce a thickness of the part" (’227 Patent, col. 15:47-50), which could be argued to encompass any process that results in a reduction, including tapering.
  • Evidence for a Narrower Interpretation: The patent figures consistently depict a distinct, stepped structure with a clear change in thickness, not a gradual taper (e.g., ’227 Patent, FIG. 5). This could support an interpretation requiring a more defined step-down, as opposed to a sloped edge.

"first insulating sidewall" (asserted in Claim 1 of both the ’227 and ’764 Patents)

• Context and Importance: The claims require a specific multi-part sidewall structure. The infringement allegation hinges on the accused device possessing not just a sidewall, but one that can be characterized as having a "first" and "second" part. The construction of this term will be critical to mapping the claims onto the accused product's physical structure.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claims do not specify how the first and second sidewalls must be formed or of what they must be made, potentially allowing for any structure with two distinguishable adjacent insulating regions to meet the limitation.
  • Evidence for a Narrower Interpretation: The specification describes forming the first and second sidewalls in separate, distinct process steps (e.g., depositing and etching back a 10 nm film for the first sidewall, then depositing and etching back a 50 nm film for the second sidewall) (’227 Patent, col. 16:38-58). This may support a narrower construction requiring the sidewalls to be structurally distinct components resulting from separate fabrication steps.

VI. Other Allegations

Indirect Infringement

The complaint alleges inducement of infringement against all seven patents. It asserts that UMC actively encourages its customers (e.g., Qualcomm) to use the accused 22nm and 28nm manufacturing processes through its sales, engineering, and marketing efforts (Compl. ¶¶80, 96). The complaint provides a table of UMC's revenue by process node geometry to show the commercial importance and promotion of these specific technologies (Compl. p. 18).

Willful Infringement

Willfulness is alleged only for the ’425 Patent. The basis for this allegation is UMC's alleged actual knowledge of the patent since at least 2019, when the ’425 Patent was cited as a reference by the USPTO examiner during the prosecution of UMC's own U.S. Patent No. 10,510,884 (Compl. ¶177).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of evidentiary sufficiency: The complaint makes detailed claims about the nanometer-scale physical structures of the accused transistors based on "information and belief." A key question for the court will be whether the technical evidence presented, such as from electron microscopy or device teardowns, can definitively prove that the commercial products manufactured on UMC's 22/28nm nodes possess the specific multi-part sidewalls, relative film thicknesses, and stress-relief layers required by the asserted claims.
• The case will also present a question of claim scope versus manufacturing reality: The patents claim specific, discrete structural features intended to solve technical problems. The infringement theory alleges that UMC's standard manufacturing processes inherently create these features. A core question will be whether the natural results of a manufacturing process, such as a "tapered edge" on a film, fall within the scope of claim terms like "smaller thickness," or if there is a fundamental mismatch between the claimed invention and the physical reality of the accused devices.
• For the ’425 Patent, a key question will be the threshold for willfulness: The willfulness allegation is based on the ’425 Patent being cited in a file history of a UMC patent. The court will have to consider whether this citation, on its own, is sufficient to establish that UMC had the requisite knowledge of infringement to support a finding of willful misconduct under the standard set by Halo.