TurboCode LLC v. Acer Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: TurboCode LLC (Texas)
  • Defendant: Acer Inc. (Taiwan)
  • Plaintiff’s Counsel: Direction IP Law
• Case Identification: 2:25-cv-00175, E.D. Tex., 02/13/2025
• Venue Allegations: Plaintiff alleges venue is proper based on Defendant’s authorized sellers and sales representatives offering infringing products for sale throughout the judicial district at retailers including Best Buy and Walmart.
• Core Dispute: Plaintiff alleges that Defendant’s products compliant with 4G/LTE cellular standards infringe a patent related to high-speed, efficient turbo code decoder architectures.
• Technical Context: The technology concerns forward error correction in wireless communications, specifically turbo decoding, a computationally intensive process critical for reliable data transmission in 3G and 4G/LTE networks.
• Key Procedural History: The patent-in-suit was the subject of an Ex Parte Reexamination requested in 2006. A Reexamination Certificate issued in 2009, which amended the asserted claim. The scope of the amended claims, which survived reexamination, will be central to the litigation.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,813,742 - "High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture," issued November 2, 2004

The Invention Explained

• Problem Addressed: The patent’s background section describes prior art turbo code decoders as being computationally complex, power-intensive, and slow due to their reliance on numerous multiplications and additions, making them impractical for portable wireless devices. (’742 Patent, col. 1:45-61).
• The Patented Solution: The invention proposes a decoder architecture using two pipelined and serially concatenated Soft-In/Soft-Out (SISO) Log-MAP decoders. This arrangement allows the decoders to work in parallel on different stages of the decoding process, enabling iterative decoding with high throughput (a decoded output per clock cycle). By operating in the logarithmic domain, the architecture replaces complex multipliers with simpler adder circuits, reducing cost and power consumption. (’742 Patent, Abstract; col. 2:40-50).
• Technical Importance: The described architecture aimed to make high-performance turbo decoding feasible for mass-market, power-constrained 3G mobile devices by increasing decoding speed and hardware efficiency. (’742 Patent, col. 2:31-40).

Key Claims at a Glance

• The complaint asserts independent claim 6, as amended by the Ex Parte Reexamination Certificate. (Compl. ¶13).
• The essential elements of reexamined claim 6 are:
  • A method of iteratively decoding a plurality of sequences of received baseband signals, comprising:
  • providing an input buffer comprising at least three shift registers, for receiving an input signal and generating first, second, and third shifted input signals;
  • providing first and second soft decision decoders serially coupled in a circular circuit, wherein each decoder processes soft decision from the preceding decoder output data, and wherein the first decoder further receives the first and second shifted input signals from the input buffer and the second decoder further receives the third shifted input signal from the input buffer;
  • providing at least one memory module coupled to an output of each of the first and second soft decision decoders, wherein the output of the memory module associated with the second soft decision decoder is fed back as an input of the first soft decision decoder;
  • processing systematic information data and extrinsic information data using the maximum a posteriori (AP) probability algorithm, and/or logarithm approximation algorithm;
  • generating soft decision based on the maximum a posteriori (MAP) probability algorithm, and/or logarithm approximation algorithm;
  • weighing and storing soft decision information into the corresponding memory module;
  • performing, for a predetermined number of times, iterative decoding from the first to the last of multiple decoders, wherein an output from the last soft decision decoder is fed back as an input to the first soft decision decoder, then from the first to the second decoders, and propagate to the last decoder in a circular circuit.
• The complaint does not explicitly reserve the right to assert dependent claims. (Compl. ¶13).

III. The Accused Instrumentality

Product Identification

• The complaint identifies a range of Acer products with 4G/LTE connectivity, including the TravelMate Spin P4, TravelMate P4, TravelMate P2, Acer Iconia Talk S, Acer Liquid Z6, Acer Swift 3, and Acer Swift 7. The allegations also extend to any other Acer products that conform to 4G/LTE standards. (Compl. ¶13).

Functionality and Market Context

• The core accused functionality is the products' compliance with 3GPP 4G/LTE standards. (Compl. ¶13). The complaint alleges that these standards require the use of turbo coding for error correction, which in turn necessitates an iterative decoding process. (Compl. ¶¶16-17). The complaint references product announcements and specification sheets to establish that the accused products incorporate 4G LTE connectivity. (Compl. ¶15). A specification sheet for the accused Acer Iconia Talk S is provided as visual evidence of its stated support for the LTE standard. (Compl. p. 9).

IV. Analysis of Infringement Allegations

The complaint's infringement theory is that compliance with 3GPP standards for 4G/LTE necessitates the performance of the method claimed in the ’742 Patent. The complaint cites various 3GPP technical specifications to map the standard's requirements to the elements of claim 6. A diagram from 3GPP TS 136 212 illustrating the structure of a standard turbo encoder is used to infer the corresponding decoder structure. (Compl. p. 15).

'742 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central question is whether compliance with a technical standard that describes a turbo encoder (Compl. p. 15) is sufficient to prove infringement of a method claim directed to a specific decoder architecture. The complaint appears to infer the decoder's structure and operation from the standard, rather than providing direct evidence from the accused products themselves. (Compl. ¶21). This raises the question of whether the logical flow in a standards-compliant decoder necessarily maps to the "circular circuit" of "soft decision decoders" recited in the claim.
  • Technical Questions: Claim 6 recites "weighing and storing soft decision information." The complaint alleges this is met by the use of Log-Likelihood Ratios (LLRs) in standard decoding. (Compl. ¶23). A technical dispute may arise over whether calculating and buffering LLRs for HARQ constitutes "weighing" as understood in the patent, especially since this term was added during reexamination, suggesting it carries a specific technical meaning.

V. Key Claim Terms for Construction

• The Term: "soft decision decoders serially coupled in a circular circuit"

• Context and Importance: This term defines the core architecture of the claimed method. Its construction will be critical for determining whether the accused products, which implement an iterative decoding process based on 3GPP standards, fall within the scope of the claim.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The specification describes a feedback loop where the output of the second decoder (44) is fed back via memory to the first decoder (42), which could support a reading that covers any iterative process with feedback between decoding stages. (’742 Patent, FIG. 4; col. 4:22-26).
  • Evidence for a Narrower Interpretation: The patent repeatedly emphasizes a specific pipelined architecture with two distinct decoders operating concurrently to achieve high speed. (’742 Patent, Abstract; col. 2:40-50). A party could argue "circular circuit" requires this specific two-decoder hardware arrangement, not just a logical feedback loop in a single processor executing an iterative algorithm.

• The Term: "weighing... soft decision information"

• Context and Importance: This term was added to claim 6 during reexamination and thus may be a focus of claim construction. Its definition is key to whether the standard handling of LLRs in an LTE decoder meets this limitation.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent does not explicitly define "weighing." A party could argue it simply refers to the general process of assigning a soft value or probability (a "weight") to a received signal, a fundamental step in any soft-decision decoding. The patent refers to converting input data into "3-bit quantization soft-values." (’742 Patent, col. 4:36-39).
  • Evidence for a Narrower Interpretation: The term was added to distinguish the invention over prior art, suggesting it implies more than the basic generation of soft values. A party might argue it requires a specific manipulation, scaling, or adjustment of the soft decision values beyond what is inherent in a standard MAP or Log-MAP algorithm. The lack of an explicit definition in the specification may lead the court to look to the prosecution history for meaning.

VI. Other Allegations

• Indirect Infringement: The complaint makes no allegations of indirect or contributory infringement. (Compl. ¶13).
• Willful Infringement: The complaint does not contain allegations of willful infringement or a request for enhanced damages. (Compl. ¶¶26, V).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A central issue will be one of evidentiary sufficiency: Can infringement of a method claim directed to a specific decoder architecture be established by demonstrating the accused products' compliance with a 4G/LTE standard, or will Plaintiff be required to produce direct evidence of the internal hardware or software structure of Acer’s specific decoder implementation?
2. The case will likely involve a key question of claim scope: Does the term "soft decision decoders serially coupled in a circular circuit," as amended during reexamination, require the specific two-decoder pipelined hardware structure disclosed in the patent's embodiments, or can it be construed more broadly to cover the logical flow of information in a standard iterative turbo decoding process?
3. A critical technical question will be one of functional mapping: Does the standard process of calculating and buffering Log-Likelihood Ratios (LLRs) in an LTE-compliant decoder perform the specific function of "weighing and storing soft decision information" as required by the claim, a term added during patent reexamination?